133 lines
4.2 KiB
Coq
133 lines
4.2 KiB
Coq
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// Assume bus responses are well-formed, assert that bus requests are
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// well-formed.
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module tb;
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reg clk;
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reg rst_n = 1'b0;
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always @ (posedge clk)
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rst_n <= 1'b1;
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// ----------------------------------------------------------------------------
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// DUT
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(* keep *) wire [31:0] ahblm_haddr;
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(* keep *) wire ahblm_hwrite;
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(* keep *) wire ahblm_hexcl;
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(* keep *) wire [1:0] ahblm_htrans;
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(* keep *) wire [2:0] ahblm_hsize;
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(* keep *) wire [2:0] ahblm_hburst;
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(* keep *) wire [3:0] ahblm_hprot;
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(* keep *) wire ahblm_hmastlock;
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(* keep *) wire ahblm_hready;
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(* keep *) wire ahblm_hexokay;
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(* keep *) wire ahblm_hresp;
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(* keep *) wire [31:0] ahblm_hwdata;
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(* keep *) wire [31:0] ahblm_hrdata;
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localparam W_DATA = 32;
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(* keep *) wire dbg_req_halt;
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(* keep *) wire dbg_req_halt_on_reset;
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(* keep *) wire dbg_req_resume;
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(* keep *) wire dbg_halted;
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(* keep *) wire dbg_running;
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(* keep *) wire [W_DATA-1:0] dbg_data0_rdata;
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(* keep *) wire [W_DATA-1:0] dbg_data0_wdata;
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(* keep *) wire dbg_data0_wen;
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(* keep *) wire [W_DATA-1:0] dbg_instr_data;
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(* keep *) wire dbg_instr_data_vld;
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(* keep *) wire dbg_instr_data_rdy;
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(* keep *) wire dbg_instr_caught_exception;
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(* keep *) wire dbg_instr_caught_ebreak;
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(* keep *) wire [31:0] irq;
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(* keep *) wire soft_irq;
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(* keep *) wire timer_irq;
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hazard3_cpu_1port dut (
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.clk (clk),
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.rst_n (rst_n),
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.ahblm_haddr (ahblm_haddr),
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.ahblm_hwrite (ahblm_hwrite),
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.ahblm_hexcl (ahblm_hexcl),
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.ahblm_htrans (ahblm_htrans),
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.ahblm_hsize (ahblm_hsize),
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.ahblm_hburst (ahblm_hburst),
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.ahblm_hprot (ahblm_hprot),
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.ahblm_hmastlock (ahblm_hmastlock),
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.ahblm_hready (ahblm_hready),
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.ahblm_hexokay (ahblm_hexokay),
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.ahblm_hresp (ahblm_hresp),
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.ahblm_hwdata (ahblm_hwdata),
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.ahblm_hrdata (ahblm_hrdata),
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.dbg_req_halt (dbg_req_halt),
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.dbg_req_halt_on_reset (dbg_req_halt_on_reset),
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.dbg_req_resume (dbg_req_resume),
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.dbg_halted (dbg_halted),
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.dbg_running (dbg_running),
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.dbg_data0_rdata (dbg_data0_rdata),
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.dbg_data0_wdata (dbg_data0_wdata),
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.dbg_data0_wen (dbg_data0_wen),
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.dbg_instr_data (dbg_instr_data),
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.dbg_instr_data_vld (dbg_instr_data_vld),
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.dbg_instr_data_rdy (dbg_instr_data_rdy),
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.dbg_instr_caught_exception (dbg_instr_caught_exception),
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.dbg_instr_caught_ebreak (dbg_instr_caught_ebreak),
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.irq (irq),
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.soft_irq (soft_irq),
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.timer_irq (timer_irq)
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);
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// ----------------------------------------------------------------------------
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// Bus properties
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// -1 -> unconstrained, >=0 -> max length
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localparam MAX_BUS_STALL = -1;
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ahbl_slave_assumptions #(
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.MAX_BUS_STALL (MAX_BUS_STALL)
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) d_assumptions (
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.clk (clk),
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.rst_n (rst_n),
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.dst_hready_resp (ahblm_hready),
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.dst_hready (ahblm_hready),
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.dst_hresp (ahblm_hresp),
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.dst_hexokay (ahblm_hexokay),
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.dst_haddr (ahblm_haddr),
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.dst_hwrite (ahblm_hwrite),
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.dst_htrans (ahblm_htrans),
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.dst_hsize (ahblm_hsize),
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.dst_hburst (ahblm_hburst),
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.dst_hprot (ahblm_hprot),
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.dst_hmastlock (ahblm_hmastlock),
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.dst_hexcl (ahblm_hexcl),
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.dst_hwdata (ahblm_hwdata),
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.dst_hrdata (ahblm_hrdata)
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);
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ahbl_master_assertions d_assertions (
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.clk (clk),
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.rst_n (rst_n),
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.src_hready (ahblm_hready),
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.src_hresp (ahblm_hresp),
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.src_hexokay (ahblm_hexokay),
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.src_haddr (ahblm_haddr),
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.src_hwrite (ahblm_hwrite),
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.src_htrans (ahblm_htrans),
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.src_hsize (ahblm_hsize),
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.src_hburst (ahblm_hburst),
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.src_hprot (ahblm_hprot),
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.src_hmastlock (ahblm_hmastlock),
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.src_hexcl (ahblm_hexcl),
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.src_hwdata (ahblm_hwdata),
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.src_hrdata (ahblm_hrdata)
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);
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endmodule
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