Hazard3/test/formal/bus_compliance_2port/Makefile

DOTF=tb.f
TOP=tb
YOSYS_SMT_SOLVER=boolector
DEPTH=25

all: bmc

include $(SCRIPTS)/formal.mk
Add simple formal bus properties check 2021-05-30 17:19:42 +08:00			`DOTF=tb.f`
			`TOP=tb`
			`YOSYS_SMT_SOLVER=boolector`
Fix bug where an IRQ can fire during load/store dphase, followed by dphase bus exception. Result was that the exception would sample the IRQ vector PC rather than the load/store instruction PC. Fix by fencing off on in-flight dphases before asserting the IRQ. This adds a cycle of jitter to IRQs, but is required for correct operation without adding a full exception-gathering pipeline. 2021-12-08 03:24:53 +08:00			`DEPTH=25`

			`all: bmc`
Add simple formal bus properties check 2021-05-30 17:19:42 +08:00
			`include $(SCRIPTS)/formal.mk`