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Hazard3/test/sim/debug_module_vectors/tb.f

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Fix some bugs/typos in DM, add a tb to run read/write vectors against DM, confirm that GPR read/write works
2021-07-11 23:20:39 +08:00
file tb.v
list $HDL/hazard3.f
Make CPU regfile nonresettable when FPGA symbol is defined, to support BRAM inference
2021-07-13 08:10:55 +08:00
list $HDL/debug/dm/hazard3_dm.f