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Fix mcontrol.execute not being writable. Enable hardware breakpoint debug tests: Hwpb1/2, JumpHBreak, TriggerExecuteInstant

This commit is contained in:
Luke Wren 2022-08-23 00:05:03 +01:00
parent 49c2edeff8
commit 04f138ae0e
2 changed files with 13 additions and 6 deletions
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5
hdl/hazard3_triggers.v
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@ -51,6 +51,7 @@ reg tdata1_dmode [0:BREAKPOINT_TRIGGERS-1];
reg mcontrol_action [0:BREAKPOINT_TRIGGERS-1]; reg mcontrol_action [0:BREAKPOINT_TRIGGERS-1];
reg mcontrol_m [0:BREAKPOINT_TRIGGERS-1]; reg mcontrol_m [0:BREAKPOINT_TRIGGERS-1];
reg mcontrol_u [0:BREAKPOINT_TRIGGERS-1]; reg mcontrol_u [0:BREAKPOINT_TRIGGERS-1];
reg mcontrol_execute [0:BREAKPOINT_TRIGGERS-1];
reg [W_DATA-1:0] tdata2 [0:BREAKPOINT_TRIGGERS-1]; reg [W_DATA-1:0] tdata2 [0:BREAKPOINT_TRIGGERS-1];
// ---------------------------------------------------------------------------- // ----------------------------------------------------------------------------
@ -65,6 +66,7 @@ always @ (posedge clk or negedge rst_n) begin: cfg_update
mcontrol_action[i] <= 1'b0; mcontrol_action[i] <= 1'b0;
mcontrol_m[i] <= 1'b0; mcontrol_m[i] <= 1'b0;
mcontrol_u[i] <= 1'b0; mcontrol_u[i] <= 1'b0;
mcontrol_execute[i] <= 1'b0;
tdata2[i] <= {W_DATA{1'b0}}; tdata2[i] <= {W_DATA{1'b0}};
end end
end else if (cfg_wen && cfg_addr == TSELECT) begin end else if (cfg_wen && cfg_addr == TSELECT) begin
@ -77,6 +79,7 @@ always @ (posedge clk or negedge rst_n) begin: cfg_update
mcontrol_action[tselect] <= cfg_wdata[12]; mcontrol_action[tselect] <= cfg_wdata[12];
mcontrol_m[tselect] <= cfg_wdata[6]; mcontrol_m[tselect] <= cfg_wdata[6];
mcontrol_u[tselect] <= cfg_wdata[3]; mcontrol_u[tselect] <= cfg_wdata[3];
mcontrol_execute[tselect] <= cfg_wdata[2];
end else if (cfg_addr == TDATA2) begin end else if (cfg_addr == TDATA2) begin
tdata2[tselect] <= cfg_wdata; tdata2[tselect] <= cfg_wdata;
end end
@ -110,7 +113,7 @@ always @ (*) begin
1'b0, 1'b0,
1'b0, // s = 0, no S-mode 1'b0, // s = 0, no S-mode
mcontrol_u[tselect], mcontrol_u[tselect],
1'b1, // execute = 1, this is a breakpoint mcontrol_execute[tselect],
1'b0, // store = 0, this is not a watchpoint 1'b0, // store = 0, this is not a watchpoint
1'b0 // load = 0, this is not a watchpoint 1'b0 // load = 0, this is not a watchpoint
}; };

4
test/sim/riscv-tests/run-debug-tests.sh
View File

@ -28,10 +28,13 @@ DebugTurbostep \
DisconnectTest \ DisconnectTest \
DownloadTest \ DownloadTest \
EbreakTest \ EbreakTest \
Hwbp1 \
Hwbp2 \
InfoTest \ InfoTest \
InstantChangePc \ InstantChangePc \
InstantHaltTest \ InstantHaltTest \
InterruptTest \ InterruptTest \
JumpHbreak \
MemTest16 \ MemTest16 \
MemTest32 \ MemTest32 \
MemTest64 \ MemTest64 \
@ -58,6 +61,7 @@ SimpleT1Test \
SimpleV13Test \ SimpleV13Test \
StepTest \ StepTest \
TooManyHwbp \ TooManyHwbp \
TriggerExecuteInstant \
UserInterrupt \ UserInterrupt \
WriteCsrs \ WriteCsrs \
WriteGprs WriteGprs