diff --git a/hdl/hazard3_core.v b/hdl/hazard3_core.v index 844b685..c3f4d09 100644 --- a/hdl/hazard3_core.v +++ b/hdl/hazard3_core.v @@ -947,7 +947,7 @@ wire m_dphase_in_flight = xm_memop != MEMOP_NONE && xm_memop != MEMOP_AMO; wire m_delay_irq_entry = xm_delay_irq_entry_on_ls_stagex || ((xm_sleep_wfi || xm_sleep_block) && !m_sleep_stall_release); -wire m_pwr_allow_sleep; +wire m_pwr_allow_clkgate; wire m_pwr_allow_power_down; wire m_pwr_allow_sleep_on_block; wire m_wfi_wakeup_req; @@ -1002,7 +1002,7 @@ hazard3_csr #( .delay_irq_entry (m_delay_irq_entry), .mepc_in (m_exception_return_addr), - .pwr_allow_sleep (m_pwr_allow_sleep), + .pwr_allow_clkgate (m_pwr_allow_clkgate), .pwr_allow_power_down (m_pwr_allow_power_down), .pwr_allow_sleep_on_block (m_pwr_allow_sleep_on_block), .pwr_wfi_wakeup_req (m_wfi_wakeup_req), @@ -1172,7 +1172,7 @@ hazard3_power_ctrl power_ctrl ( .pwrup_ack (pwrup_ack), .clk_en (clk_en), - .allow_sleep (m_pwr_allow_sleep), + .allow_clkgate (m_pwr_allow_clkgate), .allow_power_down (m_pwr_allow_power_down), .allow_sleep_on_block (m_pwr_allow_sleep_on_block), diff --git a/hdl/hazard3_csr.v b/hdl/hazard3_csr.v index b6a1bed..047ee44 100644 --- a/hdl/hazard3_csr.v +++ b/hdl/hazard3_csr.v @@ -88,7 +88,7 @@ module hazard3_csr #( input wire [XLEN-1:0] mepc_in, // Power control signalling - output wire pwr_allow_sleep, + output wire pwr_allow_clkgate, output wire pwr_allow_power_down, output wire pwr_allow_sleep_on_block, output wire pwr_wfi_wakeup_req, @@ -404,7 +404,7 @@ end assign pwr_allow_sleep_on_block = msleep_sleeponblock; assign pwr_allow_power_down = msleep_powerdown; -assign pwr_allow_sleep = msleep_deepsleep; +assign pwr_allow_clkgate = msleep_deepsleep; // ---------------------------------------------------------------------------- // Counters diff --git a/hdl/hazard3_power_ctrl.v b/hdl/hazard3_power_ctrl.v index bcf780c..8ac408e 100644 --- a/hdl/hazard3_power_ctrl.v +++ b/hdl/hazard3_power_ctrl.v @@ -28,7 +28,7 @@ module hazard3_power_ctrl #( output reg clk_en, // Power state controls from CSRs - input wire allow_sleep, + input wire allow_clkgate, input wire allow_power_down, input wire allow_sleep_on_block, @@ -82,10 +82,10 @@ always @ (posedge clk_always_on or negedge rst_n) begin end else if (active_wake_req) begin // Skip deep sleep if it would immediately fall through. stall_release <= 1'b1; - end else if ((allow_power_down || allow_sleep) && (sleeping_on_wfi || allow_sleep_on_block)) begin + end else if ((allow_power_down || allow_clkgate) && (sleeping_on_wfi || allow_sleep_on_block)) begin if (frontend_pwrdown_ok) begin pwrup_req <= !allow_power_down; - clk_en <= !allow_sleep; + clk_en <= !allow_clkgate; state <= allow_power_down ? S_ENTER_ASLEEP : S_ASLEEP; end else begin // Stay awake until it is safe to power down (i.e. until our @@ -142,7 +142,7 @@ always @ (posedge clk_always_on or negedge rst_n) begin assert(!past_stall_release); end if (state == S_ASLEEP) begin - assert(allow_power_down || allow_sleep); + assert(allow_power_down || allow_clkgate); end end end