Add single-port bus compliance. Fix adapter not re-arbitrating following an ERROR response, causing a squashed younger load-store to remain presented to the bus.
This commit is contained in:
Luke Wren
parent
1b0e205f87
commit
0a369efc06
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@ -470,6 +470,9 @@ always @ (posedge clk) if (rst_n) begin
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// Neither of these are write-address-phase.
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if (x_amo_phase == 3'h4)
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assert($past(x_amo_phase) != 3'h2);
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// Make sure M is unstalled for passing store data through in phase 2
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if (x_amo_phase == 3'h2)
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assert(!m_stall);
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end
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`endif
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@ -769,6 +772,14 @@ always @ (posedge clk or negedge rst_n) begin
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end
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end
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`ifdef FORMAL
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always @ (posedge clk) if (rst_n) begin
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// D bus errors must always squash younger load/stores
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if ($past(bus_dph_err_d && !bus_dph_ready_d))
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assert(!bus_aph_req_d);
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end
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`endif
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// Datapath flops
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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@ -152,7 +152,7 @@ always @ (posedge clk or negedge rst_n) begin
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bus_hold_aph <= 1'b0;
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bus_gnt_id_prev <= 2'h0;
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end else begin
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bus_hold_aph <= ahblm_htrans[1] && !ahblm_hready;
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bus_hold_aph <= ahblm_htrans[1] && !ahblm_hready && !ahblm_hresp;
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bus_gnt_id_prev <= {bus_gnt_i, bus_gnt_d};
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end
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end
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@ -0,0 +1,8 @@
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DOTF=tb.f
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TOP=tb
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YOSYS_SMT_SOLVER=z3
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DEPTH=25
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all: bmc
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include $(SCRIPTS)/formal.mk
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@ -0,0 +1,4 @@
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file tb.v
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file ../common/ahbl_slave_assumptions.v
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file ../common/ahbl_master_assertions.v
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list $HDL/hazard3.f
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@ -0,0 +1,132 @@
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// Assume bus responses are well-formed, assert that bus requests are
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// well-formed.
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module tb;
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reg clk;
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reg rst_n = 1'b0;
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always @ (posedge clk)
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rst_n <= 1'b1;
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// ----------------------------------------------------------------------------
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// DUT
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(* keep *) wire [31:0] ahblm_haddr;
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(* keep *) wire ahblm_hwrite;
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(* keep *) wire ahblm_hexcl;
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(* keep *) wire [1:0] ahblm_htrans;
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(* keep *) wire [2:0] ahblm_hsize;
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(* keep *) wire [2:0] ahblm_hburst;
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(* keep *) wire [3:0] ahblm_hprot;
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(* keep *) wire ahblm_hmastlock;
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(* keep *) wire ahblm_hready;
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(* keep *) wire ahblm_hexokay;
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(* keep *) wire ahblm_hresp;
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(* keep *) wire [31:0] ahblm_hwdata;
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(* keep *) wire [31:0] ahblm_hrdata;
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localparam W_DATA = 32;
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(* keep *) wire dbg_req_halt;
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(* keep *) wire dbg_req_halt_on_reset;
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(* keep *) wire dbg_req_resume;
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(* keep *) wire dbg_halted;
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(* keep *) wire dbg_running;
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(* keep *) wire [W_DATA-1:0] dbg_data0_rdata;
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(* keep *) wire [W_DATA-1:0] dbg_data0_wdata;
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(* keep *) wire dbg_data0_wen;
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(* keep *) wire [W_DATA-1:0] dbg_instr_data;
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(* keep *) wire dbg_instr_data_vld;
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(* keep *) wire dbg_instr_data_rdy;
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(* keep *) wire dbg_instr_caught_exception;
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(* keep *) wire dbg_instr_caught_ebreak;
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(* keep *) wire [31:0] irq;
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(* keep *) wire soft_irq;
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(* keep *) wire timer_irq;
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hazard3_cpu_1port dut (
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.clk (clk),
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.rst_n (rst_n),
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.ahblm_haddr (ahblm_haddr),
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.ahblm_hwrite (ahblm_hwrite),
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.ahblm_hexcl (ahblm_hexcl),
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.ahblm_htrans (ahblm_htrans),
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.ahblm_hsize (ahblm_hsize),
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.ahblm_hburst (ahblm_hburst),
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.ahblm_hprot (ahblm_hprot),
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.ahblm_hmastlock (ahblm_hmastlock),
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.ahblm_hready (ahblm_hready),
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.ahblm_hexokay (ahblm_hexokay),
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.ahblm_hresp (ahblm_hresp),
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.ahblm_hwdata (ahblm_hwdata),
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.ahblm_hrdata (ahblm_hrdata),
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.dbg_req_halt (dbg_req_halt),
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.dbg_req_halt_on_reset (dbg_req_halt_on_reset),
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.dbg_req_resume (dbg_req_resume),
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.dbg_halted (dbg_halted),
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.dbg_running (dbg_running),
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.dbg_data0_rdata (dbg_data0_rdata),
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.dbg_data0_wdata (dbg_data0_wdata),
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.dbg_data0_wen (dbg_data0_wen),
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.dbg_instr_data (dbg_instr_data),
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.dbg_instr_data_vld (dbg_instr_data_vld),
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.dbg_instr_data_rdy (dbg_instr_data_rdy),
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.dbg_instr_caught_exception (dbg_instr_caught_exception),
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.dbg_instr_caught_ebreak (dbg_instr_caught_ebreak),
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.irq (irq),
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.soft_irq (soft_irq),
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.timer_irq (timer_irq)
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);
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// ----------------------------------------------------------------------------
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// Bus properties
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// -1 -> unconstrained, >=0 -> max length
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localparam MAX_BUS_STALL = -1;
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ahbl_slave_assumptions #(
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.MAX_BUS_STALL (MAX_BUS_STALL)
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) d_assumptions (
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.clk (clk),
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.rst_n (rst_n),
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.dst_hready_resp (ahblm_hready),
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.dst_hready (ahblm_hready),
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.dst_hresp (ahblm_hresp),
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.dst_hexokay (ahblm_hexokay),
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.dst_haddr (ahblm_haddr),
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.dst_hwrite (ahblm_hwrite),
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.dst_htrans (ahblm_htrans),
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.dst_hsize (ahblm_hsize),
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.dst_hburst (ahblm_hburst),
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.dst_hprot (ahblm_hprot),
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.dst_hmastlock (ahblm_hmastlock),
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.dst_hexcl (ahblm_hexcl),
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.dst_hwdata (ahblm_hwdata),
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.dst_hrdata (ahblm_hrdata)
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);
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ahbl_master_assertions d_assertions (
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.clk (clk),
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.rst_n (rst_n),
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.src_hready (ahblm_hready),
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.src_hresp (ahblm_hresp),
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.src_hexokay (ahblm_hexokay),
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.src_haddr (ahblm_haddr),
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.src_hwrite (ahblm_hwrite),
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.src_htrans (ahblm_htrans),
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.src_hsize (ahblm_hsize),
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.src_hburst (ahblm_hburst),
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.src_hprot (ahblm_hprot),
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.src_hmastlock (ahblm_hmastlock),
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.src_hexcl (ahblm_hexcl),
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.src_hwdata (ahblm_hwdata),
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.src_hrdata (ahblm_hrdata)
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);
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endmodule
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@ -1,6 +1,6 @@
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DOTF=tb.f
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TOP=tb
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YOSYS_SMT_SOLVER=boolector
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YOSYS_SMT_SOLVER=z3
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DEPTH=25
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all: bmc
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@ -53,7 +53,9 @@ localparam W_DATA = 32;
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(* keep *) wire dbg_instr_caught_exception;
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(* keep *) wire dbg_instr_caught_ebreak;
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(* keep *) wire [15:0] irq;
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(* keep *) wire [31:0] irq;
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(* keep *) wire soft_irq;
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(* keep *) wire timer_irq;
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hazard3_cpu_2port dut (
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.clk (clk),
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@ -99,7 +101,9 @@ hazard3_cpu_2port dut (
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.dbg_instr_caught_exception (dbg_instr_caught_exception),
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.dbg_instr_caught_ebreak (dbg_instr_caught_ebreak),
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.irq (irq)
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.irq (irq),
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.soft_irq (soft_irq),
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.timer_irq (timer_irq)
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);
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// ----------------------------------------------------------------------------
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@ -64,7 +64,7 @@ always @ (posedge clk) if (rst_n) begin: dst_ahbl_req_properties
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// HSIZE appropriate for bus width
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assert(8 << src_hsize <= W_DATA);
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// No deassertion or change of active request
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if ($past(src_htrans[1] && !src_hready)) begin
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if ($past(src_htrans[1] && !src_hready && !src_hresp)) begin
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assert($stable({
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src_htrans,
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src_hwrite,
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@ -1,6 +1,6 @@
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DOTF=tb.f
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TOP=tb
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YOSYS_SMT_SOLVER=boolector
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YOSYS_SMT_SOLVER=z3
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DEFINES=HAZARD3_FORMAL_REGRESSION
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include $(SCRIPTS)/formal.mk
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