Start hacking together a DM
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Luke Wren
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/**********************************************************************
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* DO WHAT THE FUCK YOU WANT TO AND DON'T BLAME US PUBLIC LICENSE *
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* Version 3, April 2008 *
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* *
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* Copyright (C) 2021 Luke Wren *
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* *
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* Everyone is permitted to copy and distribute verbatim or modified *
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* copies of this license document and accompanying software, and *
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* changing either is allowed. *
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* *
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* TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION *
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* *
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* 0. You just DO WHAT THE FUCK YOU WANT TO. *
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* 1. We're NOT RESPONSIBLE WHEN IT DOESN'T FUCKING WORK. *
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* *
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*********************************************************************/
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// RISC-V Debug Module for Hazard3
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`default_nettype none
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module hazard3_dm #(
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// Where there are multiple harts per DM, the least-indexed hart is the
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// least-significant on each concatenated hart access bus.
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parameter N_HARTS = 1,
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// Where there are multiple DMs, the address of each DM should be a
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// multiple of 'h100, so that the lower 8 bits decode correctly.
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parameter NEXT_DM_ADDR = 32'h0000_0000,
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parameter XLEN = 32, // Do not modify
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parameter W_HARTSEL = N_HARTS > 1 ? $clog2(N_HARTS) : 1 // Do not modify
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) (
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// DM is assumed to be in same clock domain as core; clock crossing
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// (if any) is inside DTM, or between DTM and DM.
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input wire clk,
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input wire rst_n,
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// APB access from Debug Transport Module
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input wire dmi_psel,
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input wire dmi_penable,
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input wire dmi_pwrite,
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input wire [7:0] dmi_paddr,
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input wire [31:0] dmi_pwdata,
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output reg [31:0] dmi_prdata,
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output wire dmi_pready,
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output wire dmi_pslverr,
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// Reset request/acknowledge. "req" is a pulse >= 1 cycle wide. "done" is
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// level-sensitive, goes high once component is out of reset.
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//
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// The "sys" reset (ndmreset) is conventionally everything apart from DM +
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// DTM, but, as per section 3.2 in 0.13.2 debug spec: "Exactly what is
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// affected by this reset is implementation dependent, as long as it is
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// possible to debug programs from the first instruction executed." So
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// this could simply be an all-hart reset.
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output wire sys_reset_req,
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input wire sys_reset_done,
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output wire [N_HARTS-1:0] hart_reset_req,
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input wire [N_HARTS-1:0] hart_reset_done,
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// Hart run/halt control
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output wire [N_HARTS-1:0] hart_req_halt,
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output wire [N_HARTS-1:0] hart_req_halt_on_reset,
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output wire [N_HARTS-1:0] hart_req_resume,
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input wire [N_HARTS-1:0] hart_halted,
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input wire [N_HARTS-1:0] hart_running,
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// Hart access to data0 CSR (assumed to be core-internal but per-hart)
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input wire [N_HARTS*XLEN-1:0] hart_data0_rdata,
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output wire [N_HARTS*XLEN-1:0] hart_data0_wdata,
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output wire [N_HARTS-1:0] hart_data0_wen,
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// Hart instruction injection
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output wire [N_HARTS*XLEN-1:0] hart_instr_data,
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output wire [N_HARTS-1:0] hart_instr_data_vld,
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input wire [N_HARTS-1:0] hart_instr_data_rdy,
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input wire [N_HARTS-1:0] hart_instr_caught_exception,
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input wire [N_HARTS-1:0] hart_instr_caught_ebreak
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);
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wire dmi_write = dmi_psel && dmi_penable && dmi_pready && dmi_pwrite;
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wire dmi_read = dmi_psel && dmi_penable && dmi_pready && !dmi_pwrite;
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assign dmi_pready = 1'b1;
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assign dmi_pslverr = 1'b0;
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// Program buffer is fixed at 2 words plus impebreak. The main thing we care
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// about is support for efficient memory block transfers using abstractauto;
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// in this case 2 words + impebreak is sufficient for RV32I, and 1 word +
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// impebreak is sufficient for RV32IC.
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localparam PROGBUF_SIZE = 2;
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// ----------------------------------------------------------------------------
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// Address constants
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localparam ADDR_DATA0 = 8'h04;
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// Other data registers not present.
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localparam ADDR_DMCONTROL = 8'h10;
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localparam ADDR_DMSTATUS = 8'h11;
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localparam ADDR_HARTINFO = 8'h12;
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// No halt summary registers (assume no more than 32 harts)
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// No array mask select registers
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localparam ADDR_ABSTRACTCS = 8'h16;
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localparam ADDR_COMMAND = 8'h17;
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localparam ADDR_ABSTRACTAUTO = 8'h18;
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localparam ADDR_CONFSTRPTR0 = 8'h19;
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localparam ADDR_CONFSTRPTR1 = 8'h1a;
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localparam ADDR_CONFSTRPTR2 = 8'h1b;
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localparam ADDR_CONFSTRPTR3 = 8'h1c;
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localparam ADDR_NEXTDM = 8'h1d;
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localparam ADDR_PROGBUF0 = 8'h20;
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localparam ADDR_PROGBUF1 = 8'h21;
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// No authentication, no system bus access
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// ----------------------------------------------------------------------------
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// Hart selection
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reg dmactive;
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// Some fiddliness to make sure we get a single-wide zero-valued signal when
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// N_HARTS == 1 (so we can use this for indexing of per-hart signals)
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reg [W_HARTSEL-1:0] hartsel;
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wire [W_HARTSEL-1:0] hartsel_next;
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generate
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if (N_HARTS > 1) begin: has_hartsel
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// only the lower 10 bits of hartsel are supported
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assign hartsel_next = dmi_write && dmi_paddr == ADDR_DMCONTROL ?
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dmi_pwdata[16 +: W_HARTSEL] : hartsel;
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end else begin: has_no_hartsel
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assign hartsel_next = 1'b0;
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end
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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hartsel <= {W_HARTSEL{1'b0}};
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end else if (!dmactive) begin
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hartsel <= {W_HARTSEL{1'b0}};
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end else begin
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hartsel <= hartsel_next;
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end
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end
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// ----------------------------------------------------------------------------
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// Run/halt/reset control
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// Normal read/write fields for dmcontrol (note some of these are per-hart
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// fields that get rotated into dmcontrol based on the current/next hartsel).
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reg [N_HARTS-1:0] dmcontrol_haltreq;
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reg [N_HARTS-1:0] dmcontrol_hartreset;
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reg [N_HARTS-1:0] dmcontrol_resethaltreq;
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reg dmcontrol_ndmreset;
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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dmactive <= 1'b0;
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dmcontrol_ndmreset <= 1'b0;
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dmcontrol_haltreq <= {N_HARTS{1'b0}};
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dmcontrol_hartreset <= {N_HARTS{1'b0}};
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dmcontrol_resethaltreq <= {N_HARTS{1'b0}};
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end else if (!dmactive) begin
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// Only dmactive is writable when !dmactive
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if (dmi_write && dmi_paddr == ADDR_DMCONTROL)
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dmactive <= dmi_pwdata[0];
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dmcontrol_ndmreset <= 1'b0;
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dmcontrol_haltreq <= {N_HARTS{1'b0}};
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dmcontrol_hartreset <= {N_HARTS{1'b0}};
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dmcontrol_resethaltreq <= {N_HARTS{1'b0}};
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end else if dmi_write && dmi_paddr == ADDR_DMCONTROL) begin
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dmactive <= dmi_pwdata[0];
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dmcontrol_ndmreset <= dmi_pwdata[1];
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dmcontrol_haltreq[hartsel_next] <= dmi_pwdata[31];
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dmcontrol_hartreset[hartsel_next] <= dmi_pwdata[29];
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// set/clear fields on this one for some reason
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dmcontrol_resethaltreq[hartsel_next] <= dmcontrol_resethaltreq[hartsel_next]
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&& !dmi_pwdata[2] || dmi_pwdata[3];
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end
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end
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assign sys_reset_req = dmcontrol_ndmreset;
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assign hart_reset_req = dmcontrol_hartreset;
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assign hart_req_halt = dmcontrol_haltreq;
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assign hart_req_halt_on_reset = dmcontrol_resethaltreq;
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reg [N_HARTS-1:0] hart_reset_done_prev;
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reg [N_HARTS-1:0] dmstatus_havereset;
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wire [N_HARTS-1:0] hart_available = hart_reset_done & {N_HARTS{sys_reset_done}};
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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hart_reset_done_prev <= {N_HARTS{1'b0}};
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end else begin
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hart_reset_done_prev <= hart_reset_done;
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end
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end
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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dmstatus_havereset <= {N_HARTS{1'b0}};
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end else if (!dmactive) begin
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dmstatus_havereset <= {N_HARTS{1'b0}};
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end else begin
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dmstatus_havereset <= dmstatus_havereset | (hart_reset_done & ~hart_reset_done_prev);
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// dmcontrol.ackhavereset:
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if (dmi_write && dmi_paddr == ADDR_DMCONTROL && dmi_pwdata[28])
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dmstatus_havereset[hartsel_next] <= 1'b0;
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end
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end
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reg [N_HARTS-1:0] dmstatus_resumeack;
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reg [N_HARTS-1:0] dmcontrol_resumereq_sticky;
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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dmstatus_resumeack <= {N_HARTS{1'b0}};
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dmcontrol_resumereq_sticky <= {N_HARTS{1'b0}};
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end else if (!dmactive) begin
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dmstatus_resumeack <= {N_HARTS{1'b0}};
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dmcontrol_resumereq_sticky <= {N_HARTS{1'b0}};
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end else begin
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dmstatus_resumeack <= dmstatus_resumeack | (dmcontrol_resumereq_sticky & hart_running);
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dmcontrol_resumereq_sticky <= dmcontrol_resumereq_sticky & ~hart_running;
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// dmcontrol.resumereq:
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if (dmi_write && dmi_paddr == ADDR_DMCONTROL && dmi_pwdata[30]) begin
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dmcontrol_resumereq_sticky[hartsel_next] <= 1'b1;
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dmstatus_resumeack[hartsel_next] <= 1'b0;
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end
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end
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end
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assign hart_req_resume = ~dmstatus_resumeack;
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// ----------------------------------------------------------------------------
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// Abstract command data registers
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wire abstractcs_busy;
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assign hart_data0_wdata = {N_HARTS{dmi_pwdata}};
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assign hart_data0_wen = {{N_HARTS-1{1'b0}}, dmi_write && dmi_paddr == ADDR_DATA0 && !abstractcs_busy} << hartsel;
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reg [XLEN-1:0] progbuf0;
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reg [XLEN-1:0] progbuf1;
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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progbuf0 <= {XLEN{1'b0}};
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progbuf1 <= {XLEN{1'b0}};
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end else if (!dmactive) begin
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progbuf0 <= {XLEN{1'b0}};
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progbuf1 <= {XLEN{1'b0}};
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end else if (dmi_write && !abstractcs_busy) begin
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if (dmi_paddr == ADDR_PROGBUF0)
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progbuf0 <= dmi_pwdata;
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if (dmi_paddr == ADDR_PROGBUF1)
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progbuf1 <= dmi_pwdata;
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end
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end
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// We only support abstractauto on data0 update (use case is bulk memory read/write)
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reg abstractauto_autoexecdata;
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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abstractauto_autoexecdata <= 1'b0;
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end else if (!dmactive) begin
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abstractauto_autoexecdata <= 1'b0;
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end else if (dmi_write && dmi_paddr == ADDR_ABSTRACTAUTO) begin
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abstractauto_autoexecdata <= pwdata[1];
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end
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end
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// ----------------------------------------------------------------------------
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// Abstract command state machine
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localparam W_STATE = 4;
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localparam S_IDLE = 4'd0;
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localparam S_ISSUE_REGREAD = 4'd1;
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localparam S_ISSUE_REGWRITE = 4'd2;
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localparam S_ISSUE_REGEBREAK = 4'd3;
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localparam S_WAIT_REGEBREAK = 4'd4;
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localparam S_ISSUE_PROGBUF0 = 4'd5;
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localparam S_ISSUE_PROGBUF1 = 4'd6;
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localparam S_ISSUE_IMPEBREAK = 4'd7;
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localparam S_WAIT_IMPEBREAK = 4'd8;
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localparam CMDERR_OK = 3'h0;
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localparam CMDERR_BUSY = 3'h1;
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localparam CMDERR_UNSUPPORTED = 3'h2;
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localparam CMDERR_EXCEPTION = 3'h3;
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localparam CMDERR_HALTRESUME = 3'h4;
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reg [2:0] abstractcs_cmderr;
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reg [W_STATE-1:0] acmd_state;
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assign abstracts_busy = acmd_state != S_IDLE;
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wire start_abstract_cmd = abstractcs_cmderr == CMDERR_OK && !abstractcs_busy && (
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(dmi_write && dmi_paddr == ADDR_COMMAND) ||
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((dmi_write || dmi_read) && abstractauto_autoexecdata && dmi_paddr == ADDR_DATA0
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);
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wire dmi_access_illegal_when_busy =
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(dmi_write && (
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dmi_paddr == ADDR_ABSTRACTCS || dmi_paddr == ADDR_COMMAND || dmi_paddr == ADDR_ABSTRACTAUTO ||
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dmi_paddr == ADDR_DATA0 || dmi_paddr == ADDR_PROGBUF0 || dmi_paddr == ADDR_PROGBUF0)) ||
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(dmi_read && (
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dmi_paddr == ADDR_DATA0 || dmi_paddr == ADDR_PROGBUF0 || dmi_paddr == ADDR_PROGBUF0));
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wire acmd_unsupported =
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dmi_pwdata[31:24] != 8'h00 || // Only Access Register command supported
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dmi_pwdata[22:20] != 3'h2 || // Must be 32 bits in size
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dmi_pwdata[19] || // aarpostincrement not supported
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dmi_pwdata[15:12] != 4'h1 || // Only core register access supported
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dmi_pwdata[11:5] != 7'h0; // Only GPRs supported
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wire acmd_postexec = dmi_pwdata[18];
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wire acmd_transfer = dmi_pwdata[17];
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wire acmd_write = dmi_pwdata[16];
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wire [4:0] acmd_regno = dmi_pwdata[4:0]
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reg acmd_postexec_r;
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reg [4:0] acmd_regno_r;
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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abstractcs_cmderr <= CMDERR_OK;
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abstractcs_state <= S_IDLE;
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acmd_postexec_r <= 1'b0;
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acmd_regno_r <= 5'h0;
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end else if (!dmactive) begin
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abstractcs_cmderr <= CMDERR_OK;
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abstractcs_state <= S_IDLE;
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end else begin
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if (abstractcs_cmderr == CMDERR_OK && abstracts_busy && dmi_access_illegal_when_busy)
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abstractcs_cmderr <= CMDERR_BUSY;
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if (state != S_IDLE && hart_instr_caught_exception)
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abstractcs_cmderr <= CMDERR_EXCEPTION;
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case (acmd_state)
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S_IDLE: begin
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if (start_abstract_cmd) begin
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if (!hart_halted[hartsel] || !hart_available[hartsel]) begin
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abstracts_cmderr <= CMDERR_HALTRESUME;
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end else if (acmd_unsupported)
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abstractcs_cmderr <= CMDERR_UNSUPPORTED;
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end else begin
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acmd_postexec_r <= acmd_postexec;
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acmd_regno_r <= acmd_regno;
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if (acmd_transfer && acmd_write)
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state <= S_ISSUE_REGWRITE;
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else if (acmd_transfer && !acmd_write)
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state <= S_ISSUE_REGREAD;
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else if (acmd_postexec)
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state <= S_ISSUE_PROGBUF0;
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else
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state <= S_IDLE;
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end
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end
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end
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S_ISSUE_REGREAD: begin
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if (hart_instr_data_rdy[hartsel])
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state <= S_ISSUE_REGEBREAK;
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end
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S_ISSUE_REGWRITE: begin
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if (hart_instr_data_rdy[hartsel])
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state <= S_ISSUE_REGEBREAK;
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end
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S_ISSUE_REGEBREAK: begin
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if (hart_instr_data_rdy[hartsel])
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state <= S_WAIT_REGEBREAK
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end
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S_WAIT_REGEBREAK: begin
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if (hart_instr_caught_ebreak) begin
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if (acmd_postexec_r)
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state <= S_ISSUE_PROGBUF0;
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else
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state <= S_IDLE;
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end
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end
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S_ISSUE_PROGBUF0: begin
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if (hart_instr_data_rdy[hartsel])
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state <= S_ISSUE_PROGBUF1;
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end
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S_ISSUE_PROGBUF1: begin
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if (hart_instr_caught_exception || hart_instr_caught_ebreak) begin
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state <= S_IDLE;
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end else if (hart_instr_data_rdy[hartsel]) begin
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state <= S_ISSUE_IMPEBREAK;
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end
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end
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S_ISSUE_IMPEBREAK: begin
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if (hart_instr_caught_exception || hart_instr_caught_ebreak) begin
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state <= S_IDLE;
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end else if (hart_instr_data_rdy[hartsel]) begin
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state <= S_WAIT_IMPEBREAK;
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end
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end
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S_WAIT_IMPEBREAK: begin
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if (hart_instr_caught_exception || hart_instr_caught_ebreak) begin
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state <= S_IDLE;
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end
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end
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endcase
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||||
end
|
||||
end
|
||||
|
||||
assign hart_instr_data_vld = {{N_HARTS{1'b0}},
|
||||
state == S_ISSUE_REGREAD || state == S_ISSUE_REGWRITE || state == S_ISSUE_REGEBREAK ||
|
||||
state == S_ISSUE_PROGBUF0 || state == S_ISSUE_PROGBUF1 || state == S_ISSUE_IMPEBREAK
|
||||
} << hartsel;
|
||||
|
||||
assign hart_instr_data = {N_HARTS{
|
||||
state == S_ISSUE_REGWRITE ? 32'h7b202073 | {20'd0, acmd_regno_r, 7'd0} : // csrr xx, data0
|
||||
state == S_ISSUE_REGREAD ? 32'h7b201073 | {12'd0, acmd_regno_r, 15'd0} : // csrw data0, xx
|
||||
state == S_ISSUE_PROGBUF0 ? progbuf0 :
|
||||
state == S_ISSUE_PROGBUF1 ? progbuf1 :
|
||||
32'h00100073 // ebreak
|
||||
}};
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
// DMI read data mux
|
||||
always @ (*) begin
|
||||
case (dmi_paddr)
|
||||
ADDR_DATA0: dmi_prdata = hart_data0_rdata[hartsel * XLEN +: XLEN];
|
||||
ADDR_DMCONTROL: dmi_prdata = {
|
||||
dmcontrol_haltreq[hartsel],
|
||||
1'b0, // resumereq is a W1 field
|
||||
dmcontrol_hartreset[hartsel],
|
||||
1'b0, // ackhavereset is a W1 field
|
||||
1'b0, // reserved
|
||||
1'b0, // hasel hardwired 0 (no array mask)
|
||||
{{10-W_HARTSEL{1'b0}}, hartsel} // hartsello
|
||||
10'h0, // hartselhi
|
||||
2'h0, // reserved
|
||||
2'h0, // set/clrresethaltreq are W1 fields
|
||||
dmcontrol_ndmreset,
|
||||
dmactive
|
||||
};
|
||||
ADDR_DMSTATUS: dmi_prdata = {
|
||||
9'h0, // reserved
|
||||
1'b1, // impebreak = 1
|
||||
2'h0, // reserved
|
||||
{2{dmstatus_havereset[hartsel]}}, // allhavereset, anyhavereset
|
||||
{2{dmstatus_resumeack[hartsel]}}, // allresumeack, anyresumeack
|
||||
{2{hartsel >= N_HARTS}}, // allnonexistent, anynonexistent
|
||||
{2{!hart_available[hartsel}}, // allunavail, anyunavail
|
||||
{2{hart_running[hartsel]}}, // allrunning, anyrunning
|
||||
{2{hart_halted[hartsel]}}, // allhalted, anyhalted
|
||||
1'b1, // authenticated
|
||||
1'b0, // authbusy
|
||||
1'b1, // hasresethaltreq = 1 (we do support it)
|
||||
1'b0, // confstrptrvalid
|
||||
4'd2 // version = 2: RISC-V debug spec 0.13.2
|
||||
};
|
||||
ADDR_HARTINFO: dmi_prdata = {
|
||||
8'h0, // reserved
|
||||
4'h0, // nscratch = 0
|
||||
3'h0, // reserved
|
||||
1'b0, // dataccess = 0, data0 is backed by a per-hart CSR
|
||||
4'h1, // datasize = 1, a single data CSR (data0) is available
|
||||
12'h7b2 // dataaddr, same location where dscratch0 would be if implemented
|
||||
};
|
||||
ADDR_ABSTRACTCS: dmi_prdata = {
|
||||
3'h0, // reserved
|
||||
5'd2, // progbufsize = 2
|
||||
11'h0, // reserved
|
||||
abstractcs_busy,
|
||||
1'b0,
|
||||
abstractcs_cmderr,
|
||||
4'h0,
|
||||
4'd1 // datacount = 1
|
||||
};
|
||||
ADDR_ABSTRACTAUTO: dmi_prdata = {
|
||||
31'h0,
|
||||
abstractauto_autoexecdata // only data0 supported
|
||||
};
|
||||
ADDR_CONFSTRPTR0: dmi_prdata = 32'h4c296328;
|
||||
ADDR_CONFSTRPTR1: dmi_prdata = 32'h20656b75;
|
||||
ADDR_CONFSTRPTR2: dmi_prdata = 32'h6e657257;
|
||||
ADDR_CONFSTRPTR3: dmi_prdata = 32'h31322720;
|
||||
ADDR_NEXTDM: dmi_prdata = NEXT_DM_ADDR;
|
||||
ADDR_PROGBUF0: dmi_prdata = progbuf0;
|
||||
ADDR_PROGBUF1: dmi_prdata = progbuf1;
|
||||
default: dmi_prdata = {XLEN{1'b0}};
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
Loading…
Reference in New Issue