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Add U-mode and PMP to readme

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Luke Wren 2022-05-24 20:40:00 +01:00
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@ -10,8 +10,11 @@ Hazard3 is a 3-stage RISC-V processor, implementing the `RV32I` instruction set
* `Zbb`: basic bit manipulation * `Zbb`: basic bit manipulation
* `Zbc`: carry-less multiplication * `Zbc`: carry-less multiplication
* `Zbs`: single-bit manipulation * `Zbs`: single-bit manipulation
* `Zbkb`: basic bit manipulation for scalar cryptography
* M-mode privileged instructions `ECALL`, `EBREAK`, `MRET` and the `WFI` instruction * M-mode privileged instructions `ECALL`, `EBREAK`, `MRET` and the `WFI` instruction
* The machine-mode (M-mode) privilege state, and standard M-mode CSRs * The machine-mode (M-mode) privilege state, and standard M-mode CSRs
* The user-mode (U-mode) privilege state *(experimental)*
* Physical memory protection (PMP) with up to 16 naturally aligned regions *(experimental)*
* Debug support, compliant with RISC-V debug specification version 0.13.2 * Debug support, compliant with RISC-V debug specification version 0.13.2
You can [read the documentation here](doc/hazard3.pdf). (PDF link) You can [read the documentation here](doc/hazard3.pdf). (PDF link)