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tb: remove the WIDE_TIMER_IRQ flag in favour of always having the same tb interface. Second timer IRQ is ignored in single-core tb. Also, fix hmaster not being connected, which Verilator complains about.

This commit is contained in:
Luke Wren 2024-05-27 12:24:54 +01:00
parent 5b31e26790
commit 141da55507
4 changed files with 9 additions and 12 deletions
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2
test/sim/tb_cxxrtl/Makefile
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@ -18,8 +18,6 @@ SYNTH_CMD += read_verilog -I ../../../hdl -DCONFIG_HEADER="config_$(CONFIG).vh"
SYNTH_CMD += hierarchy -top $(TOP); SYNTH_CMD += hierarchy -top $(TOP);
SYNTH_CMD += write_cxxrtl build-$(DOTF)/dut.cpp SYNTH_CMD += write_cxxrtl build-$(DOTF)/dut.cpp
CDEFINES_tb_multicore.f := WIDE_TIMER_IRQ
build-$(DOTF)/dut.cpp: $(shell listfiles $(DOTF)) $(wildcard *.vh) build-$(DOTF)/dut.cpp: $(shell listfiles $(DOTF)) $(wildcard *.vh)
mkdir -p build-$(DOTF) mkdir -p build-$(DOTF)
yosys -p '$(SYNTH_CMD)' 2>&1 > build-$(DOTF)/cxxrtl.log yosys -p '$(SYNTH_CMD)' 2>&1 > build-$(DOTF)/cxxrtl.log

9
test/sim/tb_cxxrtl/tb.cpp
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@ -77,16 +77,7 @@ struct mem_io_state {
void step(cxxrtl_design::p_tb &tb) { void step(cxxrtl_design::p_tb &tb) {
// Default update logic for mtime, mtimecmp // Default update logic for mtime, mtimecmp
++mtime; ++mtime;
// This wire is 1-bit wide on single-core tb, and two bits wide on
// multicore tb. Using a set<uint8_t> on the single-core tb results
// in bit 8 of mip impossibly being set (bit 7 is the timer IRQ, bit
// 8 is hardwired to 0). Seems like a CXXRTL bug but no smaller repro
// yet, so use an ifdef for now.
#ifdef WIDE_TIMER_IRQ
tb.p_timer__irq.set<uint8_t>((mtime >= mtimecmp[0]) | (mtime >= mtimecmp[1]) << 1); tb.p_timer__irq.set<uint8_t>((mtime >= mtimecmp[0]) | (mtime >= mtimecmp[1]) << 1);
#else
tb.p_timer__irq.set<bool>(mtime >= mtimecmp[0]);
#endif
} }
}; };

6
test/sim/tb_cxxrtl/tb.v
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@ -27,6 +27,7 @@ module tb #(
output wire [2:0] i_hburst, output wire [2:0] i_hburst,
output wire [3:0] i_hprot, output wire [3:0] i_hprot,
output wire i_hmastlock, output wire i_hmastlock,
output wire [7:0] i_hmaster,
input wire i_hready, input wire i_hready,
input wire i_hresp, input wire i_hresp,
input wire i_hexokay, input wire i_hexokay,
@ -42,6 +43,7 @@ module tb #(
output wire [2:0] d_hburst, output wire [2:0] d_hburst,
output wire [3:0] d_hprot, output wire [3:0] d_hprot,
output wire d_hmastlock, output wire d_hmastlock,
output wire [7:0] d_hmaster,
input wire d_hready, input wire d_hready,
input wire d_hresp, input wire d_hresp,
input wire d_hexokay, input wire d_hexokay,
@ -51,7 +53,7 @@ module tb #(
// Level-sensitive interrupt sources // Level-sensitive interrupt sources
input wire [NUM_IRQS-1:0] irq, // -> mip.meip input wire [NUM_IRQS-1:0] irq, // -> mip.meip
input wire [1:0] soft_irq, // -> mip.msip input wire [1:0] soft_irq, // -> mip.msip
input wire timer_irq // -> mip.mtip input wire [1:0] timer_irq // -> mip.mtip
); );
// JTAG-DTM IDCODE, selected after TAP reset, would normally be a // JTAG-DTM IDCODE, selected after TAP reset, would normally be a
@ -262,6 +264,7 @@ hazard3_cpu_2port #(
.i_hburst (i_hburst), .i_hburst (i_hburst),
.i_hprot (i_hprot), .i_hprot (i_hprot),
.i_hmastlock (i_hmastlock), .i_hmastlock (i_hmastlock),
.i_hmaster (i_hmaster),
.i_hready (i_hready), .i_hready (i_hready),
.i_hresp (i_hresp), .i_hresp (i_hresp),
.i_hwdata (i_hwdata), .i_hwdata (i_hwdata),
@ -275,6 +278,7 @@ hazard3_cpu_2port #(
.d_hburst (d_hburst), .d_hburst (d_hburst),
.d_hprot (d_hprot), .d_hprot (d_hprot),
.d_hmastlock (d_hmastlock), .d_hmastlock (d_hmastlock),
.d_hmaster (d_hmaster),
.d_hready (d_hready), .d_hready (d_hready),
.d_hresp (d_hresp), .d_hresp (d_hresp),
.d_hexokay (d_hexokay), .d_hexokay (d_hexokay),

4
test/sim/tb_cxxrtl/tb_multicore.v
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@ -27,6 +27,7 @@ module tb #(
output wire [2:0] i_hburst, output wire [2:0] i_hburst,
output wire [3:0] i_hprot, output wire [3:0] i_hprot,
output wire i_hmastlock, output wire i_hmastlock,
output wire [7:0] i_hmaster,
input wire i_hready, input wire i_hready,
input wire i_hresp, input wire i_hresp,
input wire i_hexokay, input wire i_hexokay,
@ -42,6 +43,7 @@ module tb #(
output wire [2:0] d_hburst, output wire [2:0] d_hburst,
output wire [3:0] d_hprot, output wire [3:0] d_hprot,
output wire d_hmastlock, output wire d_hmastlock,
output wire [7:0] d_hmaster,
input wire d_hready, input wire d_hready,
input wire d_hresp, input wire d_hresp,
input wire d_hexokay, input wire d_hexokay,
@ -244,6 +246,7 @@ hazard3_cpu_1port #(
.hburst (i_hburst), .hburst (i_hburst),
.hprot (i_hprot), .hprot (i_hprot),
.hmastlock (i_hmastlock), .hmastlock (i_hmastlock),
.hmaster (i_hmaster),
.hready (i_hready), .hready (i_hready),
.hresp (i_hresp), .hresp (i_hresp),
.hexokay (i_hexokay), .hexokay (i_hexokay),
@ -304,6 +307,7 @@ hazard3_cpu_1port #(
.hburst (d_hburst), .hburst (d_hburst),
.hprot (d_hprot), .hprot (d_hprot),
.hmastlock (d_hmastlock), .hmastlock (d_hmastlock),
.hmaster (d_hmaster),
.hready (d_hready), .hready (d_hready),
.hresp (d_hresp), .hresp (d_hresp),
.hexokay (d_hexokay), .hexokay (d_hexokay),