Add bitmanip reference vectors and test scripts. Fix bug in bclr implementation
This commit is contained in:
Luke Wren
parent
6f1a10724b
commit
14a4f1a281
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@ -1,6 +1,6 @@
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# Hazard3
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Hazard3 is a 3-stage RISC-V processor, implementing the `RV32I` base instruction set and, optionally, the following extensions:
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Hazard3 is a 3-stage RISC-V processor, implementing the `RV32I` instruction set and the following optional extensions:
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* `M`: integer multiply/divide/modulo
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* `C`: compressed instructions
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@ -9,7 +9,6 @@ Hazard3 is a 3-stage RISC-V processor, implementing the `RV32I` base instruction
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* `Zbb`: basic bit manipulation
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* `Zbc`: carry-less multiplication
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* `Zbs`: single-bit manipulation
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* _Support for the `Zba`/`Zbb`/`Zbc`/`Zbs` bit manipulation extensions is tentative, as there are no upstream compliance tests for these at time of writing._
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* M-mode privileged instructions `ECALL`, `EBREAK`, `MRET` and the `WFI` instruction
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* The machine-mode (M-mode) privilege state, and standard M-mode CSRs
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* Debug support, compliant with RISC-V debug specification version 0.13.2
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@ -20,6 +19,8 @@ This repository also contains a compliant RISC-V Debug Module for Hazard3, which
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There is an [example SoC integration](example_soc/soc/example_soc.v), showing how these components can be assembled to create a minimal system with a JTAG-enabled RISC-V processor, some RAM and a serial port.
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_Note: the bit manipulation instructions don't have upstream compliance tests at time of writing. See [here](test/sim/bitmanip-random) for my constrained-random bitmanip tests run against spike, the RISC-V ISA simulator._
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The following are planned for future implementation:
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* `A` extension: atomic memory access
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@ -196,7 +196,7 @@ always @ (*) begin
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// Zbs
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{4'bzzz1, ALUOP_BCLR }: result = op_a & ~zbs_mask;
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{4'bzzz1, ALUOP_BSET }: result = op_a | zbs_mask;
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{4'bzzz1, ALUOP_BINV }: result = op_a ^ ~zbs_mask;
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{4'bzzz1, ALUOP_BINV }: result = op_a ^ zbs_mask;
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{4'bzzz1, ALUOP_BEXT }: result = {{W_DATA-1{1'b0}}, shift_dout[0]};
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default: result = bitwise;
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@ -67,12 +67,12 @@ localparam RV_DIVU = 32'b0000001??????????101?????0110011;
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localparam RV_REM = 32'b0000001??????????110?????0110011;
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localparam RV_REMU = 32'b0000001??????????111?????0110011;
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// B extension 1.0 rc: (Zba, Zbb, Zbc, Zbs)
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// Zba (address generation)
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localparam RV_SH1ADD = 32'b0010000??????????010?????0110011;
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localparam RV_SH2ADD = 32'b0010000??????????100?????0110011;
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localparam RV_SH3ADD = 32'b0010000??????????110?????0110011;
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// Zbb (basic bit manipulation
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// Zbb (basic bit manipulation)
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localparam RV_ANDN = 32'b0100000??????????111?????0110011;
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localparam RV_CLZ = 32'b011000000000?????001?????0010011;
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localparam RV_CPOP = 32'b011000000010?????001?????0010011;
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@ -91,10 +91,12 @@ localparam RV_SEXT_B = 32'b011000000100?????001?????0010011;
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localparam RV_SEXT_H = 32'b011000000101?????001?????0010011;
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localparam RV_XNOR = 32'b0100000??????????100?????0110011;
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localparam RV_ZEXT_H = 32'b000010000000?????100?????0110011;
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// Zbc (carry-less multiply)
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localparam RV_CLMUL = 32'b0000101??????????001?????0110011;
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localparam RV_CLMULH = 32'b0000101??????????011?????0110011;
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localparam RV_CLMULR = 32'b0000101??????????010?????0110011;
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// Zbs (single-bit manipulation)
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localparam RV_BCLR = 32'b0100100??????????001?????0110011;
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localparam RV_BCLRI = 32'b0100100??????????001?????0010011;
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@ -1 +1,2 @@
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test
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refgen
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BIN_ARCH = rv32imc_zba_zbb_zbc_zbs
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SIM_EXEC = ../tb_cxxrtl/tb
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CROSS_PREFIX = /opt/riscv/bin/riscv32-unknown-elf-
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SPIKE = spike
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PK = $(RISCV)/riscv32-unknown-elf/bin/pk
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TESTLIST=$(patsubst %.S,%,$(patsubst test/%,%,$(wildcard test/*.S)))
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.PHONY: all testall makerefs clean cleanrefs $(addprefix test-,$(TESTLIST)) $(addprefix ref-,$(TESTLIST))
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all: testall
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define make-test-target
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test-$1:
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mkdir -p tmp
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$(CROSS_PREFIX)gcc -I include -T memmap.ld -nostartfiles -march=$(BIN_ARCH) test/$1.S -o tmp/$1.elf
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$(CROSS_PREFIX)objdump -h tmp/$1.elf > tmp/$1.dis
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$(CROSS_PREFIX)objdump -d tmp/$1.elf >> tmp/$1.dis
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$(CROSS_PREFIX)objdump -j .testdata -d tmp/$1.elf >> tmp/$1.dis
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$(CROSS_PREFIX)objcopy -O binary tmp/$1.elf tmp/$1.bin
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$(SIM_EXEC) tmp/$1.bin tmp/$1.vcd --dump 0x400000 0x410000 > tmp/$1.log
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../riscv-compliance/compare_testvec tmp/$1.log reference/$1.reference_output
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endef
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# Creating reference vectors requires a recent `spike` to be installed on your PATH.
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define make-reference-target
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ref-$1:
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mkdir -p reference
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@echo "Reference for $1"
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$(CROSS_PREFIX)gcc -march=$(BIN_ARCH) -o tmp/spike-$1 refgen/$1.c
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$(SPIKE) --isa=$(BIN_ARCH) $(PK) tmp/spike-$1 | tail -n +2 > reference/$1.reference_output
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endef
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$(foreach test,$(TESTLIST),$(eval $(call make-test-target,$(test))))
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$(foreach test,$(TESTLIST),$(eval $(call make-reference-target,$(test))))
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testall: $(addprefix test-,$(TESTLIST))
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makerefs: $(addprefix ref-,$(TESTLIST))
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clean:
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rm -rf tmp/
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cleanrefs:
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rm -rf reference/
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@ -7,3 +7,26 @@ So, generate some constrained-random input vectors, and run them against the [re
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People on the mailing lists seem to defer to spike over the pseudocode in the spec anyway, so that is probably a better verification target than trying to write my own vectors based on my own interpretation of the spec.
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The Python script `vector-gen` creates two directories:
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- `test/` -- this contains assembly programs suitable for running on the Hazard3 CXXRTL testbench.
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- There is one test for each of the instructions in `Zba`/`Zbb`/`Zbc`/`Zbs`
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- The tests put a series of test values through that instruction, and write the results out to a test signature data section
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- The testbench is told to dump the signature section for comparison with the reference vectors
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- `refgen/` this contains C programs suitable for running on the `spike` ISA simulator against the RISC-V proxy kernel `pk`
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- These put the same inputs through the same instructions (using inline asm), and then `printf` the results
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- The resulting reference vectors can be found here in the `reference/` directory. They're checked in so that you don't have to install spike/pk to run these tests.
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To run all the tests and compare the results against the reference vectors, run
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```bash
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./vector-gen
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make testall
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```
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To regenerate the reference vectors using the ISA simulator, run
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```bash
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./vector-gen
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make makerefs
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```
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@ -0,0 +1,41 @@
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MEMORY
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{
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RAM (wx) : ORIGIN = 0x00000000, LENGTH = 4M
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RESULT (w) : ORIGIN = ORIGIN(RAM) + LENGTH(RAM), LENGTH = 256k
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}
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OUTPUT_FORMAT("elf32-littleriscv", "elf32-littleriscv", "elf32-littleriscv")
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OUTPUT_ARCH(riscv)
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ENTRY(_start)
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SECTIONS
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{
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.text : {
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. = ORIGIN(RAM) + 0xc0;
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PROVIDE (_start = .);
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*(.text*)
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. = ALIGN(4);
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} > RAM
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.rodata : {
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*(.rodata*)
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. = ALIGN(4);
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} > RAM
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.data : {
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*(.data*)
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. = ALIGN(4);
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} > RAM
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.bss : {
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*(.bss .bss.*)
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. = ALIGN(4);
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} > RAM
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/* Link testout section to upper memory region */
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.testdata :
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{
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PROVIDE(__testdata_start = .);
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*(.testdata)
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} > RESULT
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}
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00001000
|
||||
00002000
|
||||
00004000
|
||||
00008000
|
||||
00000001
|
||||
00000002
|
||||
00000004
|
||||
00000008
|
||||
00000010
|
||||
00000020
|
||||
00000040
|
||||
00000080
|
||||
ffffffff
|
||||
feffffff
|
||||
fdffffff
|
||||
fbffffff
|
||||
f7ffffff
|
||||
efffffff
|
||||
dfffffff
|
||||
bfffffff
|
||||
7fffffff
|
||||
fffeffff
|
||||
fffdffff
|
||||
fffbffff
|
||||
fff7ffff
|
||||
ffefffff
|
||||
ffdfffff
|
||||
ffbfffff
|
||||
ff7fffff
|
||||
fffffeff
|
||||
fffffdff
|
||||
fffffbff
|
||||
fffff7ff
|
||||
ffffefff
|
||||
ffffdfff
|
||||
ffffbfff
|
||||
ffff7fff
|
||||
fffffffe
|
||||
fffffffd
|
||||
fffffffb
|
||||
fffffff7
|
||||
ffffffef
|
||||
ffffffdf
|
||||
ffffffbf
|
||||
ffffff7f
|
||||
1099c9d9
|
||||
ae38aa12
|
||||
4f05b4fd
|
||||
cf305c0f
|
||||
d9b44822
|
||||
c7edaa14
|
||||
1a8096bd
|
||||
cc9a7a41
|
||||
3e85a902
|
||||
7bc10c2f
|
||||
70fd1298
|
||||
d2068575
|
||||
42558da4
|
||||
af2f98a6
|
||||
224ce556
|
||||
85a01a39
|
||||
53a2ae26
|
||||
543fc0d2
|
||||
8b7736a4
|
||||
b260eb1e
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,86 @@
|
|||
00000000
|
||||
00000001
|
||||
00000002
|
||||
00000004
|
||||
00000008
|
||||
00000010
|
||||
00000020
|
||||
00000040
|
||||
ffffff80
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
ffffffff
|
||||
fffffffe
|
||||
fffffffd
|
||||
fffffffb
|
||||
fffffff7
|
||||
ffffffef
|
||||
ffffffdf
|
||||
ffffffbf
|
||||
0000007f
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffbd
|
||||
00000075
|
||||
00000038
|
||||
ffffffca
|
||||
00000033
|
||||
0000002a
|
||||
0000006d
|
||||
00000016
|
||||
0000007c
|
||||
ffffffda
|
||||
ffffff93
|
||||
00000035
|
||||
ffffffdb
|
||||
00000041
|
||||
00000075
|
||||
00000043
|
||||
ffffffda
|
||||
0000006c
|
||||
ffffff81
|
||||
ffffffdf
|
||||
|
|
@ -0,0 +1,86 @@
|
|||
00000000
|
||||
00000001
|
||||
00000002
|
||||
00000004
|
||||
00000008
|
||||
00000010
|
||||
00000020
|
||||
00000040
|
||||
00000080
|
||||
00000100
|
||||
00000200
|
||||
00000400
|
||||
00000800
|
||||
00001000
|
||||
00002000
|
||||
00004000
|
||||
ffff8000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
ffffffff
|
||||
fffffffe
|
||||
fffffffd
|
||||
fffffffb
|
||||
fffffff7
|
||||
ffffffef
|
||||
ffffffdf
|
||||
ffffffbf
|
||||
ffffff7f
|
||||
fffffeff
|
||||
fffffdff
|
||||
fffffbff
|
||||
fffff7ff
|
||||
ffffefff
|
||||
ffffdfff
|
||||
ffffbfff
|
||||
00007fff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
00002c5a
|
||||
fffff706
|
||||
ffffe6d7
|
||||
ffffc83a
|
||||
0000669f
|
||||
ffff818e
|
||||
ffffab6a
|
||||
ffffff22
|
||||
0000500a
|
||||
ffffb439
|
||||
00007152
|
||||
ffffaf20
|
||||
ffffa301
|
||||
fffff18d
|
||||
00005c5a
|
||||
fffface9
|
||||
ffffa121
|
||||
00003c98
|
||||
ffffefdc
|
||||
000033e5
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,86 @@
|
|||
00000000
|
||||
00000001
|
||||
00000002
|
||||
00000004
|
||||
00000008
|
||||
00000010
|
||||
00000020
|
||||
00000040
|
||||
00000080
|
||||
00000100
|
||||
00000200
|
||||
00000400
|
||||
00000800
|
||||
00001000
|
||||
00002000
|
||||
00004000
|
||||
00008000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
0000ffff
|
||||
0000fffe
|
||||
0000fffd
|
||||
0000fffb
|
||||
0000fff7
|
||||
0000ffef
|
||||
0000ffdf
|
||||
0000ffbf
|
||||
0000ff7f
|
||||
0000feff
|
||||
0000fdff
|
||||
0000fbff
|
||||
0000f7ff
|
||||
0000efff
|
||||
0000dfff
|
||||
0000bfff
|
||||
00007fff
|
||||
0000ffff
|
||||
0000ffff
|
||||
0000ffff
|
||||
0000ffff
|
||||
0000ffff
|
||||
0000ffff
|
||||
0000ffff
|
||||
0000ffff
|
||||
0000ffff
|
||||
0000ffff
|
||||
0000ffff
|
||||
0000ffff
|
||||
0000ffff
|
||||
0000ffff
|
||||
0000ffff
|
||||
0000ffff
|
||||
000046f1
|
||||
00007acf
|
||||
00009d24
|
||||
000057a4
|
||||
00000f7a
|
||||
0000e191
|
||||
0000b3de
|
||||
000042db
|
||||
0000b7a4
|
||||
0000e047
|
||||
000040e5
|
||||
0000c45c
|
||||
00006dcf
|
||||
0000e945
|
||||
0000a77d
|
||||
00004988
|
||||
000019e4
|
||||
0000d629
|
||||
0000d0d4
|
||||
0000d72e
|
||||
|
|
@ -59,11 +59,10 @@ instr_reg_imm = [
|
|||
("bseti" , [*all_onehot0_neg, *get_random()], all_shamt),
|
||||
]
|
||||
|
||||
# Generate output files
|
||||
# Generate input vector programs
|
||||
|
||||
prolog = """
|
||||
.option norelax
|
||||
.section .text
|
||||
|
||||
// Automatically-generated test vector. Don't edit.
|
||||
|
||||
|
|
@ -72,6 +71,8 @@ prolog = """
|
|||
#define IO_PRINT_U32 (IO_BASE + 0x4)
|
||||
#define IO_EXIT (IO_BASE + 0x8)
|
||||
|
||||
.section .text
|
||||
|
||||
.global _start
|
||||
_start:
|
||||
la sp, test_signature_start
|
||||
|
|
@ -79,11 +80,23 @@ _start:
|
|||
"""
|
||||
|
||||
interlude = """
|
||||
|
||||
// Hazard3 sim returns exit status if you do this:
|
||||
|
||||
test_end:
|
||||
li a0, IO_EXIT
|
||||
sw zero, (a0)
|
||||
|
||||
.section .data
|
||||
// Catch other simulators with or without debug support:
|
||||
|
||||
la a0, it_dead
|
||||
csrw mtvec, a0
|
||||
.p2align 2
|
||||
it_dead:
|
||||
ebreak
|
||||
j it_dead
|
||||
|
||||
.section .testdata, "wa"
|
||||
|
||||
.p2align 2
|
||||
.global test_signature_start
|
||||
|
|
@ -99,15 +112,19 @@ def sanitise(name):
|
|||
return "".join(c if ("_" + c).isidentifier() else "_" for c in name)
|
||||
|
||||
Path("test").mkdir(exist_ok = True)
|
||||
Path("refgen").mkdir(exist_ok = True)
|
||||
|
||||
for instr, data in instr_one_operand:
|
||||
with open(f"test/{sanitise(instr)}.S", "w") as f:
|
||||
f.write(prolog)
|
||||
i = 0
|
||||
for d in data:
|
||||
f.write(f"test{i}:\n")
|
||||
f.write(f"\tli a1, 0x{d:08x}\n")
|
||||
f.write(f"\t{instr} a0, a1\n")
|
||||
f.write( "\tsw a0, (sp)\n")
|
||||
f.write(f"\taddi sp, sp, {XLEN // 8}\n\n")
|
||||
i = i + 1
|
||||
f.write(interlude)
|
||||
# Label the output locations for easier debug
|
||||
i = 0
|
||||
|
|
@ -120,13 +137,16 @@ for instr, data in instr_one_operand:
|
|||
for instr, rs1_list, rs2_list in instr_reg_reg:
|
||||
with open(f"test/{sanitise(instr)}.S", "w") as f:
|
||||
f.write(prolog)
|
||||
i = 0
|
||||
for rs1 in rs1_list:
|
||||
for rs2 in rs2_list:
|
||||
f.write(f"test{i}:\n")
|
||||
f.write(f"\tli a1, 0x{rs1:08x}\n")
|
||||
f.write(f"\tli a2, 0x{rs2:08x}\n")
|
||||
f.write(f"\t{instr} a0, a1, a2\n")
|
||||
f.write( "\tsw a0, (sp)\n")
|
||||
f.write(f"\taddi sp, sp, {XLEN // 8}\n\n")
|
||||
i = i + 1
|
||||
f.write(interlude)
|
||||
i = 0
|
||||
for rs1 in rs1_list:
|
||||
|
|
@ -139,12 +159,15 @@ for instr, rs1_list, rs2_list in instr_reg_reg:
|
|||
for instr, rs1_list, imm_list in instr_reg_imm:
|
||||
with open(f"test/{sanitise(instr)}.S", "w") as f:
|
||||
f.write(prolog)
|
||||
i = 0
|
||||
for rs1 in rs1_list:
|
||||
for imm in imm_list:
|
||||
f.write(f"test{i}:\n")
|
||||
f.write(f"\tli a1, 0x{rs1:08x}\n")
|
||||
f.write(f"\t{instr} a0, a1, 0x{imm:02x}\n")
|
||||
f.write( "\tsw a0, (sp)\n")
|
||||
f.write(f"\taddi sp, sp, {XLEN // 8}\n\n")
|
||||
i = i + 1
|
||||
f.write(interlude)
|
||||
i = 0
|
||||
for rs1 in rs1_list:
|
||||
|
|
@ -153,3 +176,53 @@ for instr, rs1_list, imm_list in instr_reg_imm:
|
|||
f.write("\t.word 0\n" if XLEN == 32 else "\tdword 0\n")
|
||||
i = i + 1
|
||||
f.write(epilog)
|
||||
|
||||
# Generate reference vector programs for running on spike + pk
|
||||
|
||||
# (I spent a while fighting spike to just be a processor + physical memory +
|
||||
# some MMIO, so I could run the same binaries, but this is easier)
|
||||
|
||||
c_prolog = """
|
||||
#include <stdio.h>
|
||||
|
||||
// Automatically-generated test vector. Don't edit.
|
||||
|
||||
int main() {
|
||||
unsigned int rd, rs1, rs2;
|
||||
"""
|
||||
c_output_result = '\tprintf("%08x\\n", rd);\n\n'
|
||||
|
||||
c_epilog = """
|
||||
return 0;
|
||||
}
|
||||
"""
|
||||
|
||||
for instr, data in instr_one_operand:
|
||||
with open(f"refgen/{sanitise(instr)}.c", "w") as f:
|
||||
f.write(c_prolog)
|
||||
for d in data:
|
||||
f.write(f"\trs1 = 0x{d:08x};\n");
|
||||
f.write(f'\tasm("{instr} %0, %1" : "=r" (rd) : "r" (rs1));\n')
|
||||
f.write(c_output_result)
|
||||
f.write(c_epilog)
|
||||
|
||||
for instr, rs1_list, rs2_list in instr_reg_reg:
|
||||
with open(f"refgen/{sanitise(instr)}.c", "w") as f:
|
||||
f.write(c_prolog)
|
||||
for rs1 in rs1_list:
|
||||
for rs2 in rs2_list:
|
||||
f.write(f"\trs1 = 0x{rs1:08x};\n");
|
||||
f.write(f"\trs2 = 0x{rs2:08x};\n");
|
||||
f.write(f'\tasm("{instr} %0, %1, %2" : "=r" (rd) : "r" (rs1), "r" (rs2));\n')
|
||||
f.write(c_output_result)
|
||||
f.write(c_epilog)
|
||||
|
||||
for instr, rs1_list, imm_list in instr_reg_imm:
|
||||
with open(f"refgen/{sanitise(instr)}.c", "w") as f:
|
||||
f.write(c_prolog)
|
||||
for rs1 in rs1_list:
|
||||
for imm in imm_list:
|
||||
f.write(f"\trs1 = 0x{rs1:08x};\n");
|
||||
f.write(f'\tasm("{instr} %0, %1, %2" : "=r" (rd) : "r" (rs1), "i" ({imm}));\n')
|
||||
f.write(c_output_result)
|
||||
f.write(c_epilog)
|
||||
|
|
|
|||
Loading…
Reference in New Issue