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Add bitmanip reference vectors and test scripts. Fix bug in bclr implementation

This commit is contained in:
Luke Wren 2021-11-27 17:19:34 +00:00
parent 6f1a10724b
commit 14a4f1a281
40 changed files with 207454 additions and 8 deletions
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5
Readme.md
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@ -1,6 +1,6 @@
# Hazard3 # Hazard3
Hazard3 is a 3-stage RISC-V processor, implementing the `RV32I` base instruction set and, optionally, the following extensions: Hazard3 is a 3-stage RISC-V processor, implementing the `RV32I` instruction set and the following optional extensions:
* `M`: integer multiply/divide/modulo * `M`: integer multiply/divide/modulo
* `C`: compressed instructions * `C`: compressed instructions
@ -9,7 +9,6 @@ Hazard3 is a 3-stage RISC-V processor, implementing the `RV32I` base instruction
* `Zbb`: basic bit manipulation * `Zbb`: basic bit manipulation
* `Zbc`: carry-less multiplication * `Zbc`: carry-less multiplication
* `Zbs`: single-bit manipulation * `Zbs`: single-bit manipulation
* _Support for the `Zba`/`Zbb`/`Zbc`/`Zbs` bit manipulation extensions is tentative, as there are no upstream compliance tests for these at time of writing._
* M-mode privileged instructions `ECALL`, `EBREAK`, `MRET` and the `WFI` instruction * M-mode privileged instructions `ECALL`, `EBREAK`, `MRET` and the `WFI` instruction
* The machine-mode (M-mode) privilege state, and standard M-mode CSRs * The machine-mode (M-mode) privilege state, and standard M-mode CSRs
* Debug support, compliant with RISC-V debug specification version 0.13.2 * Debug support, compliant with RISC-V debug specification version 0.13.2
@ -20,6 +19,8 @@ This repository also contains a compliant RISC-V Debug Module for Hazard3, which
There is an [example SoC integration](example_soc/soc/example_soc.v), showing how these components can be assembled to create a minimal system with a JTAG-enabled RISC-V processor, some RAM and a serial port. There is an [example SoC integration](example_soc/soc/example_soc.v), showing how these components can be assembled to create a minimal system with a JTAG-enabled RISC-V processor, some RAM and a serial port.
_Note: the bit manipulation instructions don't have upstream compliance tests at time of writing. See [here](test/sim/bitmanip-random) for my constrained-random bitmanip tests run against spike, the RISC-V ISA simulator._
The following are planned for future implementation: The following are planned for future implementation:
* `A` extension: atomic memory access * `A` extension: atomic memory access

2
hdl/arith/hazard3_alu.v
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@ -196,7 +196,7 @@ always @ (*) begin
// Zbs // Zbs
{4'bzzz1, ALUOP_BCLR }: result = op_a & ~zbs_mask; {4'bzzz1, ALUOP_BCLR }: result = op_a & ~zbs_mask;
{4'bzzz1, ALUOP_BSET }: result = op_a | zbs_mask; {4'bzzz1, ALUOP_BSET }: result = op_a | zbs_mask;
{4'bzzz1, ALUOP_BINV }: result = op_a ^ ~zbs_mask; {4'bzzz1, ALUOP_BINV }: result = op_a ^ zbs_mask;
{4'bzzz1, ALUOP_BEXT }: result = {{W_DATA-1{1'b0}}, shift_dout[0]}; {4'bzzz1, ALUOP_BEXT }: result = {{W_DATA-1{1'b0}}, shift_dout[0]};
default: result = bitwise; default: result = bitwise;

6
hdl/rv_opcodes.vh
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@ -67,12 +67,12 @@ localparam RV_DIVU = 32'b0000001??????????101?????0110011;
localparam RV_REM = 32'b0000001??????????110?????0110011; localparam RV_REM = 32'b0000001??????????110?????0110011;
localparam RV_REMU = 32'b0000001??????????111?????0110011; localparam RV_REMU = 32'b0000001??????????111?????0110011;
// B extension 1.0 rc: (Zba, Zbb, Zbc, Zbs)
// Zba (address generation) // Zba (address generation)
localparam RV_SH1ADD = 32'b0010000??????????010?????0110011; localparam RV_SH1ADD = 32'b0010000??????????010?????0110011;
localparam RV_SH2ADD = 32'b0010000??????????100?????0110011; localparam RV_SH2ADD = 32'b0010000??????????100?????0110011;
localparam RV_SH3ADD = 32'b0010000??????????110?????0110011; localparam RV_SH3ADD = 32'b0010000??????????110?????0110011;
// Zbb (basic bit manipulation
// Zbb (basic bit manipulation)
localparam RV_ANDN = 32'b0100000??????????111?????0110011; localparam RV_ANDN = 32'b0100000??????????111?????0110011;
localparam RV_CLZ = 32'b011000000000?????001?????0010011; localparam RV_CLZ = 32'b011000000000?????001?????0010011;
localparam RV_CPOP = 32'b011000000010?????001?????0010011; localparam RV_CPOP = 32'b011000000010?????001?????0010011;
@ -91,10 +91,12 @@ localparam RV_SEXT_B = 32'b011000000100?????001?????0010011;
localparam RV_SEXT_H = 32'b011000000101?????001?????0010011; localparam RV_SEXT_H = 32'b011000000101?????001?????0010011;
localparam RV_XNOR = 32'b0100000??????????100?????0110011; localparam RV_XNOR = 32'b0100000??????????100?????0110011;
localparam RV_ZEXT_H = 32'b000010000000?????100?????0110011; localparam RV_ZEXT_H = 32'b000010000000?????100?????0110011;
// Zbc (carry-less multiply) // Zbc (carry-less multiply)
localparam RV_CLMUL = 32'b0000101??????????001?????0110011; localparam RV_CLMUL = 32'b0000101??????????001?????0110011;
localparam RV_CLMULH = 32'b0000101??????????011?????0110011; localparam RV_CLMULH = 32'b0000101??????????011?????0110011;
localparam RV_CLMULR = 32'b0000101??????????010?????0110011; localparam RV_CLMULR = 32'b0000101??????????010?????0110011;
// Zbs (single-bit manipulation) // Zbs (single-bit manipulation)
localparam RV_BCLR = 32'b0100100??????????001?????0110011; localparam RV_BCLR = 32'b0100100??????????001?????0110011;
localparam RV_BCLRI = 32'b0100100??????????001?????0010011; localparam RV_BCLRI = 32'b0100100??????????001?????0010011;

1
test/sim/bitmanip-random/.gitignore vendored
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@ -1 +1,2 @@
test test
refgen

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test/sim/bitmanip-random/Makefile Normal file
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@ -0,0 +1,45 @@
BIN_ARCH = rv32imc_zba_zbb_zbc_zbs
SIM_EXEC = ../tb_cxxrtl/tb
CROSS_PREFIX = /opt/riscv/bin/riscv32-unknown-elf-
SPIKE = spike
PK = $(RISCV)/riscv32-unknown-elf/bin/pk
TESTLIST=$(patsubst %.S,%,$(patsubst test/%,%,$(wildcard test/*.S)))
.PHONY: all testall makerefs clean cleanrefs $(addprefix test-,$(TESTLIST)) $(addprefix ref-,$(TESTLIST))
all: testall
define make-test-target
test-$1:
mkdir -p tmp
$(CROSS_PREFIX)gcc -I include -T memmap.ld -nostartfiles -march=$(BIN_ARCH) test/$1.S -o tmp/$1.elf
$(CROSS_PREFIX)objdump -h tmp/$1.elf > tmp/$1.dis
$(CROSS_PREFIX)objdump -d tmp/$1.elf >> tmp/$1.dis
$(CROSS_PREFIX)objdump -j .testdata -d tmp/$1.elf >> tmp/$1.dis
$(CROSS_PREFIX)objcopy -O binary tmp/$1.elf tmp/$1.bin
$(SIM_EXEC) tmp/$1.bin tmp/$1.vcd --dump 0x400000 0x410000 > tmp/$1.log
../riscv-compliance/compare_testvec tmp/$1.log reference/$1.reference_output
endef
# Creating reference vectors requires a recent `spike` to be installed on your PATH.
define make-reference-target
ref-$1:
mkdir -p reference
@echo "Reference for $1"
$(CROSS_PREFIX)gcc -march=$(BIN_ARCH) -o tmp/spike-$1 refgen/$1.c
$(SPIKE) --isa=$(BIN_ARCH) $(PK) tmp/spike-$1 | tail -n +2 > reference/$1.reference_output
endef
$(foreach test,$(TESTLIST),$(eval $(call make-test-target,$(test))))
$(foreach test,$(TESTLIST),$(eval $(call make-reference-target,$(test))))
testall: $(addprefix test-,$(TESTLIST))
makerefs: $(addprefix ref-,$(TESTLIST))
clean:
rm -rf tmp/
cleanrefs:
rm -rf reference/

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test/sim/bitmanip-random/Readme.md
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@ -7,3 +7,26 @@ So, generate some constrained-random input vectors, and run them against the [re
People on the mailing lists seem to defer to spike over the pseudocode in the spec anyway, so that is probably a better verification target than trying to write my own vectors based on my own interpretation of the spec. People on the mailing lists seem to defer to spike over the pseudocode in the spec anyway, so that is probably a better verification target than trying to write my own vectors based on my own interpretation of the spec.
The Python script `vector-gen` creates two directories:
- `test/` -- this contains assembly programs suitable for running on the Hazard3 CXXRTL testbench.
- There is one test for each of the instructions in `Zba`/`Zbb`/`Zbc`/`Zbs`
- The tests put a series of test values through that instruction, and write the results out to a test signature data section
- The testbench is told to dump the signature section for comparison with the reference vectors
- `refgen/` this contains C programs suitable for running on the `spike` ISA simulator against the RISC-V proxy kernel `pk`
- These put the same inputs through the same instructions (using inline asm), and then `printf` the results
- The resulting reference vectors can be found here in the `reference/` directory. They're checked in so that you don't have to install spike/pk to run these tests.
To run all the tests and compare the results against the reference vectors, run
```bash
./vector-gen
make testall
```
To regenerate the reference vectors using the ISA simulator, run
```bash
./vector-gen
make makerefs
```

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MEMORY
{
RAM (wx) : ORIGIN = 0x00000000, LENGTH = 4M
RESULT (w) : ORIGIN = ORIGIN(RAM) + LENGTH(RAM), LENGTH = 256k
}
OUTPUT_FORMAT("elf32-littleriscv", "elf32-littleriscv", "elf32-littleriscv")
OUTPUT_ARCH(riscv)
ENTRY(_start)
SECTIONS
{
.text : {
. = ORIGIN(RAM) + 0xc0;
PROVIDE (_start = .);
*(.text*)
. = ALIGN(4);
} > RAM
.rodata : {
*(.rodata*)
. = ALIGN(4);
} > RAM
.data : {
*(.data*)
. = ALIGN(4);
} > RAM
.bss : {
*(.bss .bss.*)
. = ALIGN(4);
} > RAM
/* Link testout section to upper memory region */
.testdata :
{
PROVIDE(__testdata_start = .);
*(.testdata)
} > RESULT
}

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@ -0,0 +1,86 @@
00000020
0000001f
0000001e
0000001d
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00000001
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00000000
00000001
00000001
00000003
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00000000
00000001
00000001
00000000
00000000
00000000
00000000
00000001
00000000
00000003
00000002
00000007
00000004
00000000

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00000000
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000001
00000020
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0000000f
00000009
0000000e
00000013
0000000f
0000000a
00000011
00000011
00000012
00000012
0000000e
00000012
0000000f
0000000f
00000010

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00000020
00000000
00000001
00000002
00000003
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00000005
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00000009
0000000a
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00000001
00000001
00000001
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00000002
00000000
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00000000
00000000
00000002
00000000
00000001
00000000
00000001
00000001

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00000000
000000ff
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000000ff
000000ff
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000000ff
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00ffffff
ffffffff
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ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff

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00000000
01000000
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10000000
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00010000
00020000
00040000
00080000
00100000
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00400000
00800000
00000100
00000200
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00000800
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00000001
00000002
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00000080
ffffffff
feffffff
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f7ffffff
efffffff
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00000000
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00000000
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00000000
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test/sim/bitmanip-random/vector-gen
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@ -59,11 +59,10 @@ instr_reg_imm = [
("bseti" , [*all_onehot0_neg, *get_random()], all_shamt), ("bseti" , [*all_onehot0_neg, *get_random()], all_shamt),
] ]
# Generate output files # Generate input vector programs
prolog = """ prolog = """
.option norelax .option norelax
.section .text
// Automatically-generated test vector. Don't edit. // Automatically-generated test vector. Don't edit.
@ -72,6 +71,8 @@ prolog = """
#define IO_PRINT_U32 (IO_BASE + 0x4) #define IO_PRINT_U32 (IO_BASE + 0x4)
#define IO_EXIT (IO_BASE + 0x8) #define IO_EXIT (IO_BASE + 0x8)
.section .text
.global _start .global _start
_start: _start:
la sp, test_signature_start la sp, test_signature_start
@ -79,11 +80,23 @@ _start:
""" """
interlude = """ interlude = """
// Hazard3 sim returns exit status if you do this:
test_end: test_end:
li a0, IO_EXIT li a0, IO_EXIT
sw zero, (a0) sw zero, (a0)
.section .data // Catch other simulators with or without debug support:
la a0, it_dead
csrw mtvec, a0
.p2align 2
it_dead:
ebreak
j it_dead
.section .testdata, "wa"
.p2align 2 .p2align 2
.global test_signature_start .global test_signature_start
@ -99,15 +112,19 @@ def sanitise(name):
return "".join(c if ("_" + c).isidentifier() else "_" for c in name) return "".join(c if ("_" + c).isidentifier() else "_" for c in name)
Path("test").mkdir(exist_ok = True) Path("test").mkdir(exist_ok = True)
Path("refgen").mkdir(exist_ok = True)
for instr, data in instr_one_operand: for instr, data in instr_one_operand:
with open(f"test/{sanitise(instr)}.S", "w") as f: with open(f"test/{sanitise(instr)}.S", "w") as f:
f.write(prolog) f.write(prolog)
i = 0
for d in data: for d in data:
f.write(f"test{i}:\n")
f.write(f"\tli a1, 0x{d:08x}\n") f.write(f"\tli a1, 0x{d:08x}\n")
f.write(f"\t{instr} a0, a1\n") f.write(f"\t{instr} a0, a1\n")
f.write( "\tsw a0, (sp)\n") f.write( "\tsw a0, (sp)\n")
f.write(f"\taddi sp, sp, {XLEN // 8}\n\n") f.write(f"\taddi sp, sp, {XLEN // 8}\n\n")
i = i + 1
f.write(interlude) f.write(interlude)
# Label the output locations for easier debug # Label the output locations for easier debug
i = 0 i = 0
@ -120,13 +137,16 @@ for instr, data in instr_one_operand:
for instr, rs1_list, rs2_list in instr_reg_reg: for instr, rs1_list, rs2_list in instr_reg_reg:
with open(f"test/{sanitise(instr)}.S", "w") as f: with open(f"test/{sanitise(instr)}.S", "w") as f:
f.write(prolog) f.write(prolog)
i = 0
for rs1 in rs1_list: for rs1 in rs1_list:
for rs2 in rs2_list: for rs2 in rs2_list:
f.write(f"test{i}:\n")
f.write(f"\tli a1, 0x{rs1:08x}\n") f.write(f"\tli a1, 0x{rs1:08x}\n")
f.write(f"\tli a2, 0x{rs2:08x}\n") f.write(f"\tli a2, 0x{rs2:08x}\n")
f.write(f"\t{instr} a0, a1, a2\n") f.write(f"\t{instr} a0, a1, a2\n")
f.write( "\tsw a0, (sp)\n") f.write( "\tsw a0, (sp)\n")
f.write(f"\taddi sp, sp, {XLEN // 8}\n\n") f.write(f"\taddi sp, sp, {XLEN // 8}\n\n")
i = i + 1
f.write(interlude) f.write(interlude)
i = 0 i = 0
for rs1 in rs1_list: for rs1 in rs1_list:
@ -139,12 +159,15 @@ for instr, rs1_list, rs2_list in instr_reg_reg:
for instr, rs1_list, imm_list in instr_reg_imm: for instr, rs1_list, imm_list in instr_reg_imm:
with open(f"test/{sanitise(instr)}.S", "w") as f: with open(f"test/{sanitise(instr)}.S", "w") as f:
f.write(prolog) f.write(prolog)
i = 0
for rs1 in rs1_list: for rs1 in rs1_list:
for imm in imm_list: for imm in imm_list:
f.write(f"test{i}:\n")
f.write(f"\tli a1, 0x{rs1:08x}\n") f.write(f"\tli a1, 0x{rs1:08x}\n")
f.write(f"\t{instr} a0, a1, 0x{imm:02x}\n") f.write(f"\t{instr} a0, a1, 0x{imm:02x}\n")
f.write( "\tsw a0, (sp)\n") f.write( "\tsw a0, (sp)\n")
f.write(f"\taddi sp, sp, {XLEN // 8}\n\n") f.write(f"\taddi sp, sp, {XLEN // 8}\n\n")
i = i + 1
f.write(interlude) f.write(interlude)
i = 0 i = 0
for rs1 in rs1_list: for rs1 in rs1_list:
@ -153,3 +176,53 @@ for instr, rs1_list, imm_list in instr_reg_imm:
f.write("\t.word 0\n" if XLEN == 32 else "\tdword 0\n") f.write("\t.word 0\n" if XLEN == 32 else "\tdword 0\n")
i = i + 1 i = i + 1
f.write(epilog) f.write(epilog)
# Generate reference vector programs for running on spike + pk
# (I spent a while fighting spike to just be a processor + physical memory +
# some MMIO, so I could run the same binaries, but this is easier)
c_prolog = """
#include <stdio.h>
// Automatically-generated test vector. Don't edit.
int main() {
unsigned int rd, rs1, rs2;
"""
c_output_result = '\tprintf("%08x\\n", rd);\n\n'
c_epilog = """
return 0;
}
"""
for instr, data in instr_one_operand:
with open(f"refgen/{sanitise(instr)}.c", "w") as f:
f.write(c_prolog)
for d in data:
f.write(f"\trs1 = 0x{d:08x};\n");
f.write(f'\tasm("{instr} %0, %1" : "=r" (rd) : "r" (rs1));\n')
f.write(c_output_result)
f.write(c_epilog)
for instr, rs1_list, rs2_list in instr_reg_reg:
with open(f"refgen/{sanitise(instr)}.c", "w") as f:
f.write(c_prolog)
for rs1 in rs1_list:
for rs2 in rs2_list:
f.write(f"\trs1 = 0x{rs1:08x};\n");
f.write(f"\trs2 = 0x{rs2:08x};\n");
f.write(f'\tasm("{instr} %0, %1, %2" : "=r" (rd) : "r" (rs1), "r" (rs2));\n')
f.write(c_output_result)
f.write(c_epilog)
for instr, rs1_list, imm_list in instr_reg_imm:
with open(f"refgen/{sanitise(instr)}.c", "w") as f:
f.write(c_prolog)
for rs1 in rs1_list:
for imm in imm_list:
f.write(f"\trs1 = 0x{rs1:08x};\n");
f.write(f'\tasm("{instr} %0, %1, %2" : "=r" (rd) : "r" (rs1), "i" ({imm}));\n')
f.write(c_output_result)
f.write(c_epilog)