From 18c64bd633a0788793b98e48927e10773bc5eaf3 Mon Sep 17 00:00:00 2001 From: Luke Wren Date: Sun, 4 Sep 2022 23:56:14 +0100 Subject: [PATCH] Add no_rw_check attribute to regfile memory to avoid recent Yosys area regression --- hdl/hazard3_regfile_1w2r.v | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/hdl/hazard3_regfile_1w2r.v b/hdl/hazard3_regfile_1w2r.v index f8248b4..6393d0a 100644 --- a/hdl/hazard3_regfile_1w2r.v +++ b/hdl/hazard3_regfile_1w2r.v @@ -51,6 +51,12 @@ if (RESET_REGS) begin: real_dualport_reset end end else begin: real_dualport_noreset // This should be inference-compatible on FPGAs with dual-port BRAMs + `ifdef YOSYS + `ifdef FPGA_ICE40 + // We do not require write-to-read bypass logic on the BRAM + (* no_rw_check *) + `endif + `endif reg [W_DATA-1:0] mem [0:N_REGS-1]; always @ (posedge clk) begin