Fix bad AMO asserts. Fix hwdata instability during stalled AMO write dphase, which meant AMOs were fundamentally broken following yesterday's datapath origami
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1b0e205f87
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@ -458,10 +458,14 @@ always @ (posedge clk) if (rst_n) begin
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// Should be in resting state between AMOs
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// Should be in resting state between AMOs
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if (!d_memop_is_amo)
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if (!d_memop_is_amo)
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assert(x_amo_phase == 3'h0);
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assert(x_amo_phase == 3'h0);
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// Error phase should never block, so it can always pass to stage 3 to raise
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// Error phase should have no stage 2 blockers, so it can pass to stage 3 to
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// excepting trap entry.
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// raise exception entry. It's ok to block behind a younger instruction, but..
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if (x_amo_phase == 3'h4)
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if (x_amo_phase == 3'h4)
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assert(!x_stall);
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assert(!x_stall || m_stall);
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// ..the only way to reach AMO error phase without stage 3 clearing out should
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// be an unaligned AMO address, which goes straight to error phase.
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if (x_amo_phase == 3'h4 && m_stall)
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assert(x_unaligned_addr);
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// Error phase is either due to a bus response, or a misaligned address.
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// Error phase is either due to a bus response, or a misaligned address.
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// Neither of these are write-address-phase.
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// Neither of these are write-address-phase.
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if (x_amo_phase == 3'h4)
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if (x_amo_phase == 3'h4)
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@ -770,7 +774,10 @@ always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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if (!rst_n) begin
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xm_result <= {W_DATA{1'b0}};
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xm_result <= {W_DATA{1'b0}};
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xm_addr_align <= 2'b00;
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xm_addr_align <= 2'b00;
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end else if (!m_stall || (d_memop_is_amo && x_amo_phase == 3'h2 && bus_dph_ready_d)) begin
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end else if (!m_stall && !(|EXTENSION_A && x_amo_phase == 3'h3 && !bus_dph_ready_d)) begin
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// AMOs need special attention (of course):
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// - Steer captured read phase data in mw_result back through xm_result at end of AMO
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// - Make sure xm_result (store data) doesn't transition during stalled write dphase
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xm_result <=
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xm_result <=
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d_csr_ren ? x_csr_rdata :
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d_csr_ren ? x_csr_rdata :
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|EXTENSION_A && x_amo_phase == 3'h3 ? mw_result :
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|EXTENSION_A && x_amo_phase == 3'h3 ? mw_result :
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@ -1,19 +1,7 @@
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/******************************************************************************
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/*****************************************************************************\
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* DO WHAT THE FUCK YOU WANT TO AND DON'T BLAME US PUBLIC LICENSE *
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| Copyright (C) 2021 Luke Wren |
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* Version 3, April 2008 *
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| SPDX-License-Identifier: Apache-2.0 |
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* *
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\*****************************************************************************/
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* Copyright (C) 2021 Luke Wren *
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* *
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* Everyone is permitted to copy and distribute verbatim or modified *
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* copies of this license document and accompanying software, and *
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* changing either is allowed. *
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* *
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* TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION *
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* *
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* 0. You just DO WHAT THE FUCK YOU WANT TO. *
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* 1. We're NOT RESPONSIBLE WHEN IT DOESN'T FUCKING WORK. *
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* *
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*****************************************************************************/
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// Assert that an AHB-Lite master is relatively well-behaved
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// Assert that an AHB-Lite master is relatively well-behaved
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@ -1,19 +1,7 @@
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/******************************************************************************
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/*****************************************************************************\
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* DO WHAT THE FUCK YOU WANT TO AND DON'T BLAME US PUBLIC LICENSE *
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| Copyright (C) 2021 Luke Wren |
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* Version 3, April 2008 *
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| SPDX-License-Identifier: Apache-2.0 |
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* *
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\*****************************************************************************/
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* Copyright (C) 2021 Luke Wren *
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* *
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* Everyone is permitted to copy and distribute verbatim or modified *
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* copies of this license document and accompanying software, and *
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* changing either is allowed. *
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* *
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* TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION *
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* *
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* 0. You just DO WHAT THE FUCK YOU WANT TO. *
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* 1. We're NOT RESPONSIBLE WHEN IT DOESN'T FUCKING WORK. *
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* *
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*****************************************************************************/
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// Assumptions to constrain an AHB-Lite slave to be relatively well-behaved
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// Assumptions to constrain an AHB-Lite slave to be relatively well-behaved
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