tb: handle both ports identically. Preparing for dual core
This commit is contained in:
Luke Wren
parent
1fa0d4d442
commit
207566660d
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@ -0,0 +1,77 @@
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[*]
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[*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI
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[*] Wed Dec 15 09:37:16 2021
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[*]
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[dumpfile] "/home/luke/proj/hazard3/test/sim/tb_cxxrtl/waves.vcd"
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[dumpfile_mtime] "Wed Dec 15 09:24:58 2021"
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[dumpfile_size] 9773165
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[savefile] "/home/luke/proj/hazard3/test/sim/tb_cxxrtl/multicore.gtkw"
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[timestart] 0
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[size] 2509 1368
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[pos] -1 -1
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*-13.000000 9780 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[sst_width] 233
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[signals_width] 238
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[sst_expanded] 1
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[sst_vpaned_height] 410
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@200
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-JTAG
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@28
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tck
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tdi
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tdo
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tms
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@200
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-
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@28
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dm.hartsel
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@200
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-
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-Core 0 debug
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@28
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cpu0.dbg_req_halt
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cpu0.dbg_req_resume
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cpu0.dbg_halted
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@200
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-
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@28
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cpu0.dbg_instr_data_vld
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cpu0.dbg_instr_data_rdy
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@22
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cpu0.dbg_instr_data[31:0]
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@28
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cpu0.dbg_instr_caught_ebreak
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cpu0.dbg_instr_caught_exception
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@200
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-
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@22
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cpu0.dbg_data0_rdata[31:0]
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cpu0.dbg_data0_wdata[31:0]
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@28
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cpu0.dbg_data0_wen
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@200
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-
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-Core 1 debug
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@28
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cpu1.dbg_req_halt
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cpu1.dbg_req_resume
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cpu1.dbg_halted
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@200
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-
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@28
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cpu1.dbg_instr_data_vld
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cpu1.dbg_instr_data_rdy
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@22
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cpu1.dbg_instr_data[31:0]
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@28
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cpu1.dbg_instr_caught_ebreak
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cpu1.dbg_instr_caught_exception
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@200
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-
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@22
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cpu1.dbg_data0_rdata[31:0]
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cpu1.dbg_data0_wdata[31:0]
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@28
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cpu1.dbg_data0_wen
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[pattern_trace] 1
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[pattern_trace] 0
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@ -2,7 +2,6 @@
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#include <fstream>
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#include <cstdint>
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#include <string>
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#include <algorithm>
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#include <stdio.h>
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#include <unistd.h>
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@ -13,8 +12,9 @@
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#include "dut.cpp"
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#include <backends/cxxrtl/cxxrtl_vcd.h>
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// -----------------------------------------------------------------------------
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static const unsigned int MEM_SIZE = 16 * 1024 * 1024;
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uint8_t mem[MEM_SIZE];
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static const unsigned int IO_BASE = 0x80000000;
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enum {
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@ -31,7 +31,143 @@ enum {
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IO_MTIMECMPH = 0x10c
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};
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static const int TCP_BUF_SIZE = 256;
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struct mem_io_state {
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uint64_t mtime;
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uint64_t mtimecmp;
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bool exit_req;
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uint32_t exit_code;
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uint8_t *mem;
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mem_io_state() {
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mtime = 0;
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mtimecmp = 0;
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exit_req = false;
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exit_code = 0;
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mem = new uint8_t[MEM_SIZE];
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for (size_t i = 0; i < MEM_SIZE; ++i)
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mem[i] = 0;
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}
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// Where we're going we don't need a destructor B-)
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void step(cxxrtl_design::p_tb &tb) {
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// Default update logic for mtime, mtimecmp
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++mtime;
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tb.p_timer__irq.set<bool>(mtime >= mtimecmp);
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}
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};
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typedef enum {
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SIZE_BYTE = 0,
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SIZE_HWORD = 1,
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SIZE_WORD = 2
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} bus_size_t;
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struct bus_request {
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uint32_t addr;
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bus_size_t size;
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bool write;
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bool excl;
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uint32_t wdata;
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bus_request(): addr(0), size(SIZE_BYTE), write(0), excl(0), wdata(0) {}
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};
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struct bus_response {
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uint32_t rdata;
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int stall_cycles;
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bool err;
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bool exokay;
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bus_response(): rdata(0), stall_cycles(0), err(false), exokay(true) {}
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};
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bus_response mem_access(cxxrtl_design::p_tb &tb, mem_io_state &memio, bus_request req) {
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bus_response resp;
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if (req.write) {
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if (req.addr <= MEM_SIZE - 4u) {
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unsigned int n_bytes = 1u << (int)req.size;
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// Note we are relying on hazard3's byte lane replication
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for (unsigned int i = 0; i < n_bytes; ++i) {
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memio.mem[req.addr + i] = req.wdata >> (8 * i) & 0xffu;
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}
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}
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else if (req.addr == IO_BASE + IO_PRINT_CHAR) {
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putchar(req.wdata);
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}
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else if (req.addr == IO_BASE + IO_PRINT_U32) {
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printf("%08x\n", req.wdata);
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}
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else if (req.addr == IO_BASE + IO_EXIT) {
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if (!memio.exit_req) {
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memio.exit_req = true;
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memio.exit_code = req.wdata;
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}
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}
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else if (req.addr == IO_BASE + IO_SET_SOFTIRQ) {
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tb.p_soft__irq.set<bool>(true);
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}
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else if (req.addr == IO_BASE + IO_CLR_SOFTIRQ) {
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tb.p_soft__irq.set<bool>(false);
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}
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else if (req.addr == IO_BASE + IO_SET_IRQ) {
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tb.p_irq.set<uint32_t>(tb.p_irq.get<uint32_t>() | req.wdata);
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}
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else if (req.addr == IO_BASE + IO_CLR_IRQ) {
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tb.p_irq.set<uint32_t>(tb.p_irq.get<uint32_t>() & ~req.wdata);
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}
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else if (req.addr == IO_BASE + IO_MTIME) {
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memio.mtime = (memio.mtime & 0xffffffff00000000u) | req.wdata;
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}
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else if (req.addr == IO_BASE + IO_MTIMEH) {
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memio.mtime = (memio.mtime & 0x00000000ffffffffu) | ((uint64_t)req.wdata << 32);
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}
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else if (req.addr == IO_BASE + IO_MTIMECMP) {
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memio.mtimecmp = (memio.mtimecmp & 0xffffffff00000000u) | req.wdata;
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}
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else if (req.addr == IO_BASE + IO_MTIMECMPH) {
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memio.mtimecmp = (memio.mtimecmp & 0x00000000ffffffffu) | ((uint64_t)req.wdata << 32);
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}
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else {
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resp.err = true;
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}
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}
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else {
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if (req.addr <= MEM_SIZE - (1u << (int)req.size)) {
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req.addr &= ~0x3u;
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resp.rdata =
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(uint32_t)memio.mem[req.addr] |
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memio.mem[req.addr + 1] << 8 |
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memio.mem[req.addr + 2] << 16 |
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memio.mem[req.addr + 3] << 24;
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}
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else if (req.addr == IO_BASE + IO_SET_SOFTIRQ || req.addr == IO_BASE + IO_CLR_SOFTIRQ) {
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resp.rdata = tb.p_soft__irq.get<bool>();
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}
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else if (req.addr == IO_BASE + IO_SET_IRQ || req.addr == IO_BASE + IO_CLR_IRQ) {
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resp.rdata = tb.p_irq.get<uint32_t>();
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}
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else if (req.addr == IO_BASE + IO_MTIME) {
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resp.rdata = memio.mtime;
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}
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else if (req.addr == IO_BASE + IO_MTIMEH) {
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resp.rdata = memio.mtime >> 32;
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}
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else if (req.addr == IO_BASE + IO_MTIMECMP) {
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resp.rdata = memio.mtimecmp;
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}
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else if (req.addr == IO_BASE + IO_MTIMECMPH) {
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resp.rdata = memio.mtimecmp >> 32;
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}
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else {
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resp.err = true;
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}
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}
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return resp;
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}
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// -----------------------------------------------------------------------------
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const char *help_str =
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"Usage: tb [--bin x.bin] [--vcd x.vcd] [--dump start end] [--cycles n] [--port n]\n"
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@ -50,6 +186,8 @@ void exit_help(std::string errtext = "") {
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exit(-1);
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}
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static const int TCP_BUF_SIZE = 256;
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int main(int argc, char **argv) {
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bool load_bin = false;
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@ -109,22 +247,6 @@ int main(int argc, char **argv) {
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if (!(load_bin || port != 0))
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exit_help("At least one of --bin or --port must be specified.\n");
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std::fill(std::begin(mem), std::end(mem), 0);
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if (load_bin) {
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std::ifstream fd(bin_path, std::ios::binary | std::ios::ate);
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if (!fd){
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std::cerr << "Failed to open \"" << bin_path << "\"\n";
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return -1;
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}
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std::streamsize bin_size = fd.tellg();
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if (bin_size > MEM_SIZE) {
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std::cerr << "Binary file (" << bin_size << " bytes) is larger than memory (" << MEM_SIZE << " bytes)\n";
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return -1;
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}
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fd.seekg(0, std::ios::beg);
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fd.read((char*)mem, bin_size);
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}
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int server_fd, sock_fd;
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struct sockaddr_in sock_addr;
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int sock_opt = 1;
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@ -170,6 +292,23 @@ int main(int argc, char **argv) {
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printf("Connected\n");
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}
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mem_io_state memio;
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if (load_bin) {
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std::ifstream fd(bin_path, std::ios::binary | std::ios::ate);
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if (!fd){
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std::cerr << "Failed to open \"" << bin_path << "\"\n";
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return -1;
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}
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std::streamsize bin_size = fd.tellg();
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if (bin_size > MEM_SIZE) {
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std::cerr << "Binary file (" << bin_size << " bytes) is larger than memory (" << MEM_SIZE << " bytes)\n";
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return -1;
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}
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fd.seekg(0, std::ios::beg);
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fd.read((char*)memio.mem, bin_size);
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}
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cxxrtl_design::p_tb top;
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std::ofstream waves_fd;
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@ -182,21 +321,18 @@ int main(int argc, char **argv) {
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vcd.add(all_debug_items);
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}
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bool bus_trans = false;
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bool bus_write = false;
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bool bus_trans_i = false;
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uint32_t bus_addr_i = 0;
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uint32_t bus_addr = 0;
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uint8_t bus_size = 0;
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// Never generate bus stalls
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// Loop-carried address-phase requests
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bus_request req_i;
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bus_request req_d;
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bool req_i_vld = false;
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bool req_d_vld = false;
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// Set bus interfaces to generate good IDLE responses at first
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top.p_i__hready.set<bool>(true);
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top.p_d__hready.set<bool>(true);
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top.p_d__hexokay.set<bool>(true);
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uint64_t mtime = 0;
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uint64_t mtimecmp = 0;
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// Reset + initial clock pulse
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top.step();
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top.p_clk.set<bool>(true);
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top.p_tck.set<bool>(true);
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@ -274,107 +410,38 @@ int main(int argc, char **argv) {
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}
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}
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// Default update logic for mtime, mtimecmp
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++mtime;
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top.p_timer__irq.set<bool>(mtime >= mtimecmp);
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memio.step(top);
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// The two bus ports are handled identically. This enables swapping out of
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// various `tb.v` hardware integration files containing:
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//
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// - A single, dual-ported processor (instruction fetch, load/store ports)
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// - A single, single-ported processor (instruction fetch + load/store muxed internally)
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// - A pair of single-ported processors, for dual-core debug tests
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if (top.p_d__hready.get<bool>()) {
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// Clear bus error by default
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top.p_d__hresp.set<bool>(false);
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// Handle current data phase
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uint32_t rdata = 0;
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bool bus_err = false;
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if (bus_trans && bus_write) {
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uint32_t wdata = top.p_d__hwdata.get<uint32_t>();
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if (bus_addr <= MEM_SIZE - 4u) {
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unsigned int n_bytes = 1u << bus_size;
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// Note we are relying on hazard3's byte lane replication
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for (unsigned int i = 0; i < n_bytes; ++i) {
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mem[bus_addr + i] = wdata >> (8 * i) & 0xffu;
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}
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}
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else if (bus_addr == IO_BASE + IO_PRINT_CHAR) {
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putchar(wdata);
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}
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else if (bus_addr == IO_BASE + IO_PRINT_U32) {
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printf("%08x\n", wdata);
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}
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else if (bus_addr == IO_BASE + IO_EXIT) {
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printf("CPU requested halt. Exit code %d\n", wdata);
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printf("Ran for %ld cycles\n", cycle + 1);
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break;
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}
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else if (bus_addr == IO_BASE + IO_SET_SOFTIRQ) {
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top.p_soft__irq.set<bool>(true);
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}
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else if (bus_addr == IO_BASE + IO_CLR_SOFTIRQ) {
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top.p_soft__irq.set<bool>(false);
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}
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else if (bus_addr == IO_BASE + IO_SET_IRQ) {
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top.p_irq.set<uint32_t>(top.p_irq.get<uint32_t>() | wdata);
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}
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else if (bus_addr == IO_BASE + IO_CLR_IRQ) {
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top.p_irq.set<uint32_t>(top.p_irq.get<uint32_t>() & ~wdata);
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}
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else if (bus_addr == IO_BASE + IO_MTIME) {
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mtime = (mtime & 0xffffffff00000000u) | wdata;
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}
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else if (bus_addr == IO_BASE + IO_MTIMEH) {
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mtime = (mtime & 0x00000000ffffffffu) | ((uint64_t)wdata << 32);
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}
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else if (bus_addr == IO_BASE + IO_MTIMECMP) {
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mtimecmp = (mtimecmp & 0xffffffff00000000u) | wdata;
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}
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else if (bus_addr == IO_BASE + IO_MTIMECMPH) {
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mtimecmp = (mtimecmp & 0x00000000ffffffffu) | ((uint64_t)wdata << 32);
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}
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else {
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bus_err = true;
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}
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}
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else if (bus_trans && !bus_write) {
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if (bus_addr <= MEM_SIZE - (1u << bus_size)) {
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bus_addr &= ~0x3u;
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rdata =
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(uint32_t)mem[bus_addr] |
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mem[bus_addr + 1] << 8 |
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mem[bus_addr + 2] << 16 |
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mem[bus_addr + 3] << 24;
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}
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else if (bus_addr == IO_BASE + IO_SET_SOFTIRQ || bus_addr == IO_BASE + IO_CLR_SOFTIRQ) {
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rdata = top.p_soft__irq.get<bool>();
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}
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else if (bus_addr == IO_BASE + IO_SET_IRQ || bus_addr == IO_BASE + IO_CLR_IRQ) {
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rdata = top.p_irq.get<uint32_t>();
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}
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else if (bus_addr == IO_BASE + IO_MTIME) {
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rdata = mtime;
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}
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else if (bus_addr == IO_BASE + IO_MTIMEH) {
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rdata = mtime >> 32;
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}
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else if (bus_addr == IO_BASE + IO_MTIMECMP) {
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rdata = mtimecmp;
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}
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else if (bus_addr == IO_BASE + IO_MTIMECMPH) {
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rdata = mtimecmp >> 32;
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}
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else {
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bus_err = true;
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}
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}
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if (bus_err) {
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req_d.wdata = top.p_d__hwdata.get<uint32_t>();
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bus_response resp;
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if (req_d_vld)
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resp = mem_access(top, memio, req_d);
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if (resp.err) {
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// Phase 1 of error response
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top.p_d__hready.set<bool>(false);
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top.p_d__hresp.set<bool>(true);
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}
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top.p_d__hrdata.set<uint32_t>(rdata);
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top.p_d__hrdata.set<uint32_t>(resp.rdata);
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top.p_d__hexokay.set<bool>(resp.exokay);
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// Progress current address phase to data phase
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bus_trans = top.p_d__htrans.get<uint8_t>() >> 1;
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bus_write = top.p_d__hwrite.get<bool>();
|
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bus_size = top.p_d__hsize.get<uint8_t>();
|
||||
bus_addr = top.p_d__haddr.get<uint32_t>();
|
||||
req_d_vld = top.p_d__htrans.get<uint8_t>() >> 1;
|
||||
req_d.write = top.p_d__hwrite.get<bool>();
|
||||
req_d.size = (bus_size_t)top.p_d__hsize.get<uint8_t>();
|
||||
req_d.addr = top.p_d__haddr.get<uint32_t>();
|
||||
req_d.excl = top.p_d__hexcl.get<bool>();
|
||||
}
|
||||
else {
|
||||
// hready=0. Currently this only happens when we're in the first
|
||||
|
|
@ -382,27 +449,32 @@ int main(int argc, char **argv) {
|
|||
top.p_d__hready.set<bool>(true);
|
||||
}
|
||||
|
||||
|
||||
if (top.p_i__hready.get<bool>()) {
|
||||
top.p_i__hresp.set<bool>(false);
|
||||
if (bus_trans_i) {
|
||||
bus_addr_i &= ~0x3u;
|
||||
if (bus_addr_i < MEM_SIZE) {
|
||||
top.p_i__hrdata.set<uint32_t>(
|
||||
(uint32_t)mem[bus_addr_i] |
|
||||
mem[bus_addr_i + 1] << 8 |
|
||||
mem[bus_addr_i + 2] << 16 |
|
||||
mem[bus_addr_i + 3] << 24
|
||||
);
|
||||
}
|
||||
else {
|
||||
top.p_i__hready.set<bool>(false);
|
||||
top.p_i__hresp.set<bool>(true);
|
||||
}
|
||||
|
||||
req_i.wdata = top.p_i__hwdata.get<uint32_t>();
|
||||
bus_response resp;
|
||||
if (req_i_vld)
|
||||
resp = mem_access(top, memio, req_i);
|
||||
if (resp.err) {
|
||||
// Phase 1 of error response
|
||||
top.p_i__hready.set<bool>(false);
|
||||
top.p_i__hresp.set<bool>(true);
|
||||
}
|
||||
bus_trans_i = top.p_i__htrans.get<uint8_t>() >> 1;
|
||||
bus_addr_i = top.p_i__haddr.get<uint32_t>();
|
||||
top.p_i__hrdata.set<uint32_t>(resp.rdata);
|
||||
top.p_i__hexokay.set<bool>(resp.exokay);
|
||||
|
||||
// Progress current address phase to data phase
|
||||
req_i_vld = top.p_i__htrans.get<uint8_t>() >> 1;
|
||||
req_i.write = top.p_i__hwrite.get<bool>();
|
||||
req_i.size = (bus_size_t)top.p_i__hsize.get<uint8_t>();
|
||||
req_i.addr = top.p_i__haddr.get<uint32_t>();
|
||||
req_i.excl = top.p_i__hexcl.get<bool>();
|
||||
}
|
||||
else {
|
||||
// hready=0. Currently this only happens when we're in the first
|
||||
// phase of an error response, so go to phase 2.
|
||||
top.p_i__hready.set<bool>(true);
|
||||
}
|
||||
|
||||
|
|
@ -415,6 +487,11 @@ int main(int argc, char **argv) {
|
|||
vcd.buffer.clear();
|
||||
}
|
||||
|
||||
if (memio.exit_req) {
|
||||
printf("CPU requested halt. Exit code %d\n", memio.exit_code);
|
||||
printf("Ran for %ld cycles\n", cycle + 1);
|
||||
break;
|
||||
}
|
||||
if (cycle + 1 == max_cycles)
|
||||
printf("Max cycles reached\n");
|
||||
if (got_exit_cmd)
|
||||
|
|
@ -426,7 +503,7 @@ int main(int argc, char **argv) {
|
|||
for (auto r : dump_ranges) {
|
||||
printf("Dumping memory from %08x to %08x:\n", r.first, r.second);
|
||||
for (int i = 0; i < r.second - r.first; ++i)
|
||||
printf("%02x%c", mem[r.first + i], i % 16 == 15 ? '\n' : ' ');
|
||||
printf("%02x%c", memio.mem[r.first + i], i % 16 == 15 ? '\n' : ' ');
|
||||
printf("\n");
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -21,12 +21,14 @@ module tb #(
|
|||
output wire [W_ADDR-1:0] i_haddr,
|
||||
output wire i_hwrite,
|
||||
output wire [1:0] i_htrans,
|
||||
output wire i_hexcl,
|
||||
output wire [2:0] i_hsize,
|
||||
output wire [2:0] i_hburst,
|
||||
output wire [3:0] i_hprot,
|
||||
output wire i_hmastlock,
|
||||
input wire i_hready,
|
||||
input wire i_hresp,
|
||||
input wire i_hexokay,
|
||||
output wire [W_DATA-1:0] i_hwdata,
|
||||
input wire [W_DATA-1:0] i_hrdata,
|
||||
|
||||
|
|
@ -233,4 +235,6 @@ hazard3_cpu_2port #(
|
|||
.timer_irq (timer_irq)
|
||||
);
|
||||
|
||||
assign i_hexcl = 1'b0;
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
Loading…
Reference in New Issue