From 2618ae0c0713a8a073c034704264b31f8759d814 Mon Sep 17 00:00:00 2001 From: Luke Wren Date: Sun, 18 Jul 2021 16:03:53 +0100 Subject: [PATCH] Double-step() after clock posedge to workaround CXXRTL port propagation issue --- test/sim/openocd/tb.cpp | 2 ++ test/sim/tb_cxxrtl/tb.cpp | 2 ++ 2 files changed, 4 insertions(+) diff --git a/test/sim/openocd/tb.cpp b/test/sim/openocd/tb.cpp index 8c56a0d..5bf9a14 100644 --- a/test/sim/openocd/tb.cpp +++ b/test/sim/openocd/tb.cpp @@ -161,6 +161,7 @@ int main(int argc, char **argv) { top.p_trst__n.set(true); top.p_rst__n.set(true); top.step(); + top.step(); // workaround for github.com/YosysHQ/yosys/issues/2780 for (int64_t cycle = 0; cycle < max_cycles || max_cycles == 0; ++cycle) { top.p_clk.set(false); @@ -169,6 +170,7 @@ int main(int argc, char **argv) { vcd.sample(cycle * 2); top.p_clk.set(true); top.step(); + top.step(); // workaround for github.com/YosysHQ/yosys/issues/2780 // Most bitbang commands complete in one cycle (e.g. TCK/TMS/TDI // writes) but reads take 0 cycles, step=false. diff --git a/test/sim/tb_cxxrtl/tb.cpp b/test/sim/tb_cxxrtl/tb.cpp index d846688..f9b9e93 100644 --- a/test/sim/tb_cxxrtl/tb.cpp +++ b/test/sim/tb_cxxrtl/tb.cpp @@ -122,6 +122,7 @@ int main(int argc, char **argv) { top.p_clk.set(false); top.p_rst__n.set(true); top.step(); + top.step(); // workaround for github.com/YosysHQ/yosys/issues/2780 for (int64_t cycle = 0; cycle < max_cycles; ++cycle) { top.p_clk.set(false); @@ -130,6 +131,7 @@ int main(int argc, char **argv) { vcd.sample(cycle * 2); top.p_clk.set(true); top.step(); + top.step(); // workaround for github.com/YosysHQ/yosys/issues/2780 // Handle current data phase, then move current address phase to data phase uint32_t rdata = 0; if (bus_trans && bus_write) {