diff --git a/test/sim/riscv-tests/riscv-tests b/test/sim/riscv-tests/riscv-tests
index 0211e0d..b6ac197 160000
--- a/test/sim/riscv-tests/riscv-tests
+++ b/test/sim/riscv-tests/riscv-tests
@@ -1 +1 @@
-Subproject commit 0211e0dacc85d2fa5270e719260f060e21bcc298
+Subproject commit b6ac1971d121f25ef32dcc46f033f637a967e55f
diff --git a/test/sim/riscv-tests/run-debug-tests.sh b/test/sim/riscv-tests/run-debug-tests.sh
index e0d8a07..73f7ecd 100755
--- a/test/sim/riscv-tests/run-debug-tests.sh
+++ b/test/sim/riscv-tests/run-debug-tests.sh
@@ -17,6 +17,7 @@ done
 	--gcc riscv32-unknown-elf-gcc \
 	targets/luke/hazard3.py \
 CheckMisa \
+CrashLoop \
 DebugBreakpoint \
 DebugChangeString \
 DebugCompareSections \
@@ -28,12 +29,9 @@ DisconnectTest \
 DownloadTest \
 EbreakTest \
 InfoTest \
-InterruptTest \
-CrashLoop \
 InstantChangePc \
 InstantHaltTest \
-MemorySampleMixed \
-MemorySampleSingle \
+InterruptTest \
 MemTest16 \
 MemTest32 \
 MemTest64 \
@@ -42,12 +40,15 @@ MemTestBlock0 \
 MemTestBlock1 \
 MemTestBlock2 \
 MemTestReadInvalid \
+MemorySampleMixed \
+MemorySampleSingle \
 PrivChange \
 PrivRw \
 ProgramSwWatchpoint \
 Registers \
 RepeatReadTest \
 Semihosting \
+SemihostingFileio \
 SimpleF18Test \
 SimpleNoExistTest \
 SimpleS0Test \