From 27793b25a1f2a7374840f232863dd58b7c2e0651 Mon Sep 17 00:00:00 2001 From: Luke Wren Date: Mon, 4 Jul 2022 00:45:20 +0100 Subject: [PATCH] Rebase riscv-tests against upstream, and pick up new semihosting file io test --- test/sim/riscv-tests/riscv-tests | 2 +- test/sim/riscv-tests/run-debug-tests.sh | 9 +++++---- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/test/sim/riscv-tests/riscv-tests b/test/sim/riscv-tests/riscv-tests index 0211e0d..b6ac197 160000 --- a/test/sim/riscv-tests/riscv-tests +++ b/test/sim/riscv-tests/riscv-tests @@ -1 +1 @@ -Subproject commit 0211e0dacc85d2fa5270e719260f060e21bcc298 +Subproject commit b6ac1971d121f25ef32dcc46f033f637a967e55f diff --git a/test/sim/riscv-tests/run-debug-tests.sh b/test/sim/riscv-tests/run-debug-tests.sh index e0d8a07..73f7ecd 100755 --- a/test/sim/riscv-tests/run-debug-tests.sh +++ b/test/sim/riscv-tests/run-debug-tests.sh @@ -17,6 +17,7 @@ done --gcc riscv32-unknown-elf-gcc \ targets/luke/hazard3.py \ CheckMisa \ +CrashLoop \ DebugBreakpoint \ DebugChangeString \ DebugCompareSections \ @@ -28,12 +29,9 @@ DisconnectTest \ DownloadTest \ EbreakTest \ InfoTest \ -InterruptTest \ -CrashLoop \ InstantChangePc \ InstantHaltTest \ -MemorySampleMixed \ -MemorySampleSingle \ +InterruptTest \ MemTest16 \ MemTest32 \ MemTest64 \ @@ -42,12 +40,15 @@ MemTestBlock0 \ MemTestBlock1 \ MemTestBlock2 \ MemTestReadInvalid \ +MemorySampleMixed \ +MemorySampleSingle \ PrivChange \ PrivRw \ ProgramSwWatchpoint \ Registers \ RepeatReadTest \ Semihosting \ +SemihostingFileio \ SimpleF18Test \ SimpleNoExistTest \ SimpleS0Test \