From 279e4b4f2986b4d809dbf401931f809e738d0744 Mon Sep 17 00:00:00 2001 From: Luke Wren Date: Fri, 23 Jul 2021 21:52:01 +0100 Subject: [PATCH] Implement mstatush as hardwired-0, as required by priv-1.12 --- hdl/hazard3_csr.v | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/hdl/hazard3_csr.v b/hdl/hazard3_csr.v index db63688..b85c90e 100644 --- a/hdl/hazard3_csr.v +++ b/hdl/hazard3_csr.v @@ -115,6 +115,7 @@ localparam MHARTID = 12'hf14; // Hardware thread ID. // Machine Trap Setup (RW) localparam MSTATUS = 12'h300; // Machine status register. +localparam MSTATUSH = 12'h310; // As of priv-1.12 this must be present even if tied 0. localparam MISA = 12'h301; // ISA and extensions localparam MEDELEG = 12'h302; // Machine exception delegation register. localparam MIDELEG = 12'h303; // Machine interrupt delegation register. @@ -625,9 +626,13 @@ always @ (*) begin }; end - // MSTATUSH is not implemented (permitted when all fields would be tied to - // zero -- those fields being MBE and SBE, which are zero because we are - // pure little-endian.) + // MSTATUSH is all zeroes (fields are MBE and SBE, which are zero because + // we are pure little-endian.) Prior to priv-1.12 MSTATUSH could be left + // unimplemented in this case, but now it must be decoded even if + // hardwired to 0. + MSTATUSH: if (CSR_M_MANDATORY || CSR_M_TRAP) begin + decode_match = 1'b1; + end // MEDELEG, MIDELEG should not exist for M-only implementations. Will raise // illegal instruction exception if accessed.