Correctly implement fence.i as branch-to-next. Make Zifencei optional. Tighten up decode on fence and fence.i.
This commit is contained in:
Luke Wren
parent
35651f52a7
commit
2c8f3974d0
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@ -37,44 +37,50 @@ parameter MTVEC_INIT = 32'h00000000,
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// RISC-V ISA and CSR support
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// EXTENSION_A: Support for atomic read/modify/write instructions
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parameter EXTENSION_A = 1,
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parameter EXTENSION_A = 1,
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// EXTENSION_C: Support for compressed (variable-width) instructions
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parameter EXTENSION_C = 1,
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parameter EXTENSION_C = 1,
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// EXTENSION_M: Support for hardware multiply/divide/modulo instructions
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parameter EXTENSION_M = 1,
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parameter EXTENSION_M = 1,
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// EXTENSION_ZBA: Support for Zba address generation instructions
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parameter EXTENSION_ZBA = 1,
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parameter EXTENSION_ZBA = 1,
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// EXTENSION_ZBB: Support for Zbb basic bit manipulation instructions
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parameter EXTENSION_ZBB = 1,
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parameter EXTENSION_ZBB = 1,
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// EXTENSION_ZBC: Support for Zbc carry-less multiplication instructions
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parameter EXTENSION_ZBC = 1,
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parameter EXTENSION_ZBC = 1,
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// EXTENSION_ZBS: Support for Zbs single-bit manipulation instructions
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parameter EXTENSION_ZBS = 1,
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parameter EXTENSION_ZBS = 1,
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// EXTENSION_ZIFENCEI: Support for the fence.i instruction
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// Optional, since a plain branch/jump will also flush the prefetch queue.
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parameter EXTENSION_ZIFENCEI = 1,
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// Note the Zicsr extension is implied by any of the following CSR support:
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// CSR_M_MANDATORY: Bare minimum CSR support e.g. misa. Spec says must = 1 if
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// CSRs are present, but I won't tell anyone.
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parameter CSR_M_MANDATORY = 1,
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parameter CSR_M_MANDATORY = 1,
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// CSR_M_TRAP: Include M-mode trap-handling CSRs, and enable trap support.
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parameter CSR_M_TRAP = 1,
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parameter CSR_M_TRAP = 1,
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// CSR_COUNTER: Include performance counters and relevant M-mode CSRs
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parameter CSR_COUNTER = 1,
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parameter CSR_COUNTER = 1,
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// DEBUG_SUPPORT: Support for run/halt and instruction injection from an
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// external Debug Module, support for Debug Mode, and Debug Mode CSRs.
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// Requires: CSR_M_MANDATORY, CSR_M_TRAP.
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parameter DEBUG_SUPPORT = 0,
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parameter DEBUG_SUPPORT = 0,
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// NUM_IRQ: Number of external IRQs implemented in meie0 and meip0.
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// Minimum 1 (if CSR_M_TRAP = 1), maximum 128.
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parameter NUM_IRQ = 32,
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parameter NUM_IRQ = 32,
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// ----------------------------------------------------------------------------
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// ID registers
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@ -82,42 +88,42 @@ parameter NUM_IRQ = 32,
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// JEDEC JEP106-compliant vendor ID, can be left at 0 if "not implemented or
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// [...] this is a non-commercial implementation" (RISC-V spec).
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// 31:7 is continuation code count, 6:0 is ID. Parity bit is not stored.
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parameter MVENDORID_VAL = 32'h0,
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parameter MVENDORID_VAL = 32'h0,
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// Implementation ID for this specific version of Hazard3. Git hash is perfect.
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parameter MIMPID_VAL = 32'h0,
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parameter MIMPID_VAL = 32'h0,
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// Each core has a single hardware thread. Multiple cores should have unique IDs.
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parameter MHARTID_VAL = 32'h0,
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parameter MHARTID_VAL = 32'h0,
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// Pointer to configuration structure blob, or all-zeroes. Must be at least
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// 4-byte-aligned.
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parameter MCONFIGPTR_VAL = 32'h0,
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parameter MCONFIGPTR_VAL = 32'h0,
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// ----------------------------------------------------------------------------
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// Performance/size options
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// REDUCED_BYPASS: Remove all forwarding paths except X->X (so back-to-back
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// ALU ops can still run at 1 CPI), to save area.
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parameter REDUCED_BYPASS = 0,
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parameter REDUCED_BYPASS = 0,
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// MULDIV_UNROLL: Bits per clock for multiply/divide circuit, if present. Must
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// be a power of 2.
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parameter MULDIV_UNROLL = 1,
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parameter MULDIV_UNROLL = 1,
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// MUL_FAST: Use single-cycle multiply circuit for MUL instructions, retiring
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// to stage M. The sequential multiply/divide circuit is still used for MULH*
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parameter MUL_FAST = 0,
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parameter MUL_FAST = 0,
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// MULH_FAST: extend the fast multiply circuit to also cover MULH*, and remove
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// the multiply functionality from the sequential multiply/divide circuit.
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// Requires; MUL_FAST
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parameter MULH_FAST = 0,
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parameter MULH_FAST = 0,
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// FAST_BRANCHCMP: Instantiate a separate comparator (eq/lt/ltu) for branch
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// resolution, rather than using the ALU. May improve fetch address delay.
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// (Especially if Zba extension is enabled)
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parameter FAST_BRANCHCMP = 1,
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// comparisons, rather than using the ALU. Improves fetch address delay,
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// especially if Zba extension is enabled. Disabling may save area.
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parameter FAST_BRANCHCMP = 1,
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// MTVEC_WMASK: Mask of which bits in MTVEC are modifiable. Save gates by
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// making trap vector base partly fixed (legal, as it's WARL).
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@ -126,10 +132,10 @@ parameter FAST_BRANCHCMP = 1,
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//
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// - Note the entire vector table must always be aligned to its size, rounded
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// up to a power of two, so careful with the low-order bits.
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parameter MTVEC_WMASK = 32'hfffffffd,
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parameter MTVEC_WMASK = 32'hfffffffd,
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// ----------------------------------------------------------------------------
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// Port size parameters (do not modify)
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parameter W_ADDR = 32, // Do not modify
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parameter W_DATA = 32 // Do not modify
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parameter W_ADDR = 32, // Do not modify
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parameter W_DATA = 32 // Do not modify
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@ -7,29 +7,30 @@
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// be set at instantiation rather than editing the config file, and will flow
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// correctly down through the hierarchy.
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.RESET_VECTOR (RESET_VECTOR),
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.MTVEC_INIT (MTVEC_INIT),
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.EXTENSION_A (EXTENSION_A),
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.EXTENSION_C (EXTENSION_C),
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.EXTENSION_M (EXTENSION_M),
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.EXTENSION_ZBA (EXTENSION_ZBA),
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.EXTENSION_ZBB (EXTENSION_ZBB),
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.EXTENSION_ZBC (EXTENSION_ZBC),
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.EXTENSION_ZBS (EXTENSION_ZBS),
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.CSR_M_MANDATORY (CSR_M_MANDATORY),
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.CSR_M_TRAP (CSR_M_TRAP),
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.CSR_COUNTER (CSR_COUNTER),
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.DEBUG_SUPPORT (DEBUG_SUPPORT),
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.NUM_IRQ (NUM_IRQ),
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.MVENDORID_VAL (MVENDORID_VAL),
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.MIMPID_VAL (MIMPID_VAL),
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.MHARTID_VAL (MHARTID_VAL),
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.MCONFIGPTR_VAL (MCONFIGPTR_VAL),
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.REDUCED_BYPASS (REDUCED_BYPASS),
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.MULDIV_UNROLL (MULDIV_UNROLL),
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.MUL_FAST (MUL_FAST),
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.MULH_FAST (MULH_FAST),
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.FAST_BRANCHCMP (FAST_BRANCHCMP),
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.MTVEC_WMASK (MTVEC_WMASK),
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.W_ADDR (W_ADDR),
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.W_DATA (W_DATA)
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.RESET_VECTOR (RESET_VECTOR),
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.MTVEC_INIT (MTVEC_INIT),
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.EXTENSION_A (EXTENSION_A),
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.EXTENSION_C (EXTENSION_C),
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.EXTENSION_M (EXTENSION_M),
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.EXTENSION_ZBA (EXTENSION_ZBA),
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.EXTENSION_ZBB (EXTENSION_ZBB),
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.EXTENSION_ZBC (EXTENSION_ZBC),
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.EXTENSION_ZBS (EXTENSION_ZBS),
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.EXTENSION_ZIFENCEI (EXTENSION_ZIFENCEI),
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.CSR_M_MANDATORY (CSR_M_MANDATORY),
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.CSR_M_TRAP (CSR_M_TRAP),
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.CSR_COUNTER (CSR_COUNTER),
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.DEBUG_SUPPORT (DEBUG_SUPPORT),
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.NUM_IRQ (NUM_IRQ),
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.MVENDORID_VAL (MVENDORID_VAL),
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.MIMPID_VAL (MIMPID_VAL),
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.MHARTID_VAL (MHARTID_VAL),
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.MCONFIGPTR_VAL (MCONFIGPTR_VAL),
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.REDUCED_BYPASS (REDUCED_BYPASS),
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.MULDIV_UNROLL (MULDIV_UNROLL),
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.MUL_FAST (MUL_FAST),
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.MULH_FAST (MULH_FAST),
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.FAST_BRANCHCMP (FAST_BRANCHCMP),
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.MTVEC_WMASK (MTVEC_WMASK),
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.W_ADDR (W_ADDR),
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.W_DATA (W_DATA)
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@ -149,14 +149,15 @@ end
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always @ (*) begin
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casez ({|EXTENSION_A, d_instr[6:2]})
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{1'bz, 5'b11011}: d_addr_offs = d_imm_j ; // JAL
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{1'bz, 5'b11000}: d_addr_offs = d_imm_b ; // Branches
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{1'bz, 5'b01000}: d_addr_offs = d_imm_s ; // Store
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{1'bz, 5'b11001}: d_addr_offs = d_imm_i ; // JALR
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{1'bz, 5'b00000}: d_addr_offs = d_imm_i ; // Loads
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{1'b1, 5'b01011}: d_addr_offs = 32'h0000_0000; // Atomics
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default: d_addr_offs = 32'hxxxx_xxxx;
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casez ({|EXTENSION_A, |EXTENSION_ZIFENCEI, d_instr[6:2]})
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{1'bz, 1'bz, 5'b11011}: d_addr_offs = d_imm_j ; // JAL
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{1'bz, 1'bz, 5'b11000}: d_addr_offs = d_imm_b ; // Branches
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{1'bz, 1'bz, 5'b01000}: d_addr_offs = d_imm_s ; // Store
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{1'bz, 1'bz, 5'b11001}: d_addr_offs = d_imm_i ; // JALR
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{1'bz, 1'bz, 5'b00000}: d_addr_offs = d_imm_i ; // Loads
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{1'b1, 1'bz, 5'b01011}: d_addr_offs = 32'h0000_0000; // Atomics
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{1'bz, 1'b1, 5'b00011}: d_addr_offs = 32'h0000_0004; // Zifencei
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default: d_addr_offs = 32'hxxxx_xxxx;
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endcase
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end
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@ -282,8 +283,8 @@ always @ (*) begin
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RV_BSET: if (EXTENSION_ZBS) begin d_aluop = ALUOP_BSET; end else begin d_invalid_32bit = 1'b1; end
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RV_BSETI: if (EXTENSION_ZBS) begin d_aluop = ALUOP_BSET; d_rs2 = X0; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; end else begin d_invalid_32bit = 1'b1; end
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RV_FENCE: begin d_rd = X0; end // NOP
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RV_FENCE_I: begin d_invalid_32bit = DEBUG_SUPPORT && debug_mode; d_rd = X0; d_rs1 = X0; d_rs2 = X0; d_branchcond = BCOND_NZERO; d_imm[31] = 1'b1; end // FIXME this is probably busted now. Maybe implement as an exception?
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RV_FENCE: begin d_rs2 = X0; end // NOP, note rs1/rd are zero in instruction
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RV_FENCE_I: if (EXTENSION_ZIFENCEI) begin d_invalid_32bit = DEBUG_SUPPORT && debug_mode; d_branchcond = BCOND_ALWAYS; end else begin d_invalid_32bit = 1'b1; end // note rs1/rs2/rd are zero in instruction
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RV_CSRRW: if (HAVE_CSR) begin d_imm = d_imm_i; d_csr_wen = 1'b1 ; d_csr_ren = |d_rd; d_csr_wtype = CSR_WTYPE_W; end else begin d_invalid_32bit = 1'b1; end
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RV_CSRRS: if (HAVE_CSR) begin d_imm = d_imm_i; d_csr_wen = |d_rs1; d_csr_ren = 1'b1 ; d_csr_wtype = CSR_WTYPE_S; end else begin d_invalid_32bit = 1'b1; end
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RV_CSRRC: if (HAVE_CSR) begin d_imm = d_imm_i; d_csr_wen = |d_rs1; d_csr_ren = 1'b1 ; d_csr_wtype = CSR_WTYPE_C; end else begin d_invalid_32bit = 1'b1; end
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@ -48,8 +48,8 @@ localparam RV_LHU = 32'b?????????????????101?????0000011;
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localparam RV_SB = 32'b?????????????????000?????0100011;
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localparam RV_SH = 32'b?????????????????001?????0100011;
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localparam RV_SW = 32'b?????????????????010?????0100011;
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localparam RV_FENCE = 32'b?????????????????000?????0001111;
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localparam RV_FENCE_I = 32'b?????????????????001?????0001111;
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localparam RV_FENCE = 32'b????????????00000000000000001111;
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localparam RV_FENCE_I = 32'b00000000000000000001000000001111;
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localparam RV_ECALL = 32'b00000000000000000000000001110011;
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localparam RV_EBREAK = 32'b00000000000100000000000001110011;
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localparam RV_CSRRW = 32'b?????????????????001?????1110011;
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