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Correctly implement fence.i as branch-to-next. Make Zifencei optional. Tighten up decode on fence and fence.i.

This commit is contained in:
Luke Wren 2022-04-09 13:49:16 +01:00
parent 35651f52a7
commit 2c8f3974d0
4 changed files with 72 additions and 64 deletions
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10
hdl/hazard3_config.vh
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@ -57,6 +57,12 @@ parameter EXTENSION_ZBC = 1,
// EXTENSION_ZBS: Support for Zbs single-bit manipulation instructions
parameter EXTENSION_ZBS = 1,
// EXTENSION_ZIFENCEI: Support for the fence.i instruction
// Optional, since a plain branch/jump will also flush the prefetch queue.
parameter EXTENSION_ZIFENCEI = 1,
// Note the Zicsr extension is implied by any of the following CSR support:
// CSR_M_MANDATORY: Bare minimum CSR support e.g. misa. Spec says must = 1 if
// CSRs are present, but I won't tell anyone.
parameter CSR_M_MANDATORY = 1,
@ -115,8 +121,8 @@ parameter MUL_FAST = 0,
parameter MULH_FAST = 0,
// FAST_BRANCHCMP: Instantiate a separate comparator (eq/lt/ltu) for branch
// resolution, rather than using the ALU. May improve fetch address delay.
// (Especially if Zba extension is enabled)
// comparisons, rather than using the ALU. Improves fetch address delay,
// especially if Zba extension is enabled. Disabling may save area.
parameter FAST_BRANCHCMP = 1,
// MTVEC_WMASK: Mask of which bits in MTVEC are modifiable. Save gates by

1
hdl/hazard3_config_inst.vh
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@ -16,6 +16,7 @@
.EXTENSION_ZBB (EXTENSION_ZBB),
.EXTENSION_ZBC (EXTENSION_ZBC),
.EXTENSION_ZBS (EXTENSION_ZBS),
.EXTENSION_ZIFENCEI (EXTENSION_ZIFENCEI),
.CSR_M_MANDATORY (CSR_M_MANDATORY),
.CSR_M_TRAP (CSR_M_TRAP),
.CSR_COUNTER (CSR_COUNTER),

19
hdl/hazard3_decode.v
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@ -149,13 +149,14 @@ end
always @ (*) begin
casez ({|EXTENSION_A, d_instr[6:2]})
{1'bz, 5'b11011}: d_addr_offs = d_imm_j ; // JAL
{1'bz, 5'b11000}: d_addr_offs = d_imm_b ; // Branches
{1'bz, 5'b01000}: d_addr_offs = d_imm_s ; // Store
{1'bz, 5'b11001}: d_addr_offs = d_imm_i ; // JALR
{1'bz, 5'b00000}: d_addr_offs = d_imm_i ; // Loads
{1'b1, 5'b01011}: d_addr_offs = 32'h0000_0000; // Atomics
casez ({|EXTENSION_A, |EXTENSION_ZIFENCEI, d_instr[6:2]})
{1'bz, 1'bz, 5'b11011}: d_addr_offs = d_imm_j ; // JAL
{1'bz, 1'bz, 5'b11000}: d_addr_offs = d_imm_b ; // Branches
{1'bz, 1'bz, 5'b01000}: d_addr_offs = d_imm_s ; // Store
{1'bz, 1'bz, 5'b11001}: d_addr_offs = d_imm_i ; // JALR
{1'bz, 1'bz, 5'b00000}: d_addr_offs = d_imm_i ; // Loads
{1'b1, 1'bz, 5'b01011}: d_addr_offs = 32'h0000_0000; // Atomics
{1'bz, 1'b1, 5'b00011}: d_addr_offs = 32'h0000_0004; // Zifencei
default: d_addr_offs = 32'hxxxx_xxxx;
endcase
end
@ -282,8 +283,8 @@ always @ (*) begin
RV_BSET: if (EXTENSION_ZBS) begin d_aluop = ALUOP_BSET; end else begin d_invalid_32bit = 1'b1; end
RV_BSETI: if (EXTENSION_ZBS) begin d_aluop = ALUOP_BSET; d_rs2 = X0; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; end else begin d_invalid_32bit = 1'b1; end
RV_FENCE: begin d_rd = X0; end // NOP
RV_FENCE_I: begin d_invalid_32bit = DEBUG_SUPPORT && debug_mode; d_rd = X0; d_rs1 = X0; d_rs2 = X0; d_branchcond = BCOND_NZERO; d_imm[31] = 1'b1; end // FIXME this is probably busted now. Maybe implement as an exception?
RV_FENCE: begin d_rs2 = X0; end // NOP, note rs1/rd are zero in instruction
RV_FENCE_I: if (EXTENSION_ZIFENCEI) begin d_invalid_32bit = DEBUG_SUPPORT && debug_mode; d_branchcond = BCOND_ALWAYS; end else begin d_invalid_32bit = 1'b1; end // note rs1/rs2/rd are zero in instruction
RV_CSRRW: if (HAVE_CSR) begin d_imm = d_imm_i; d_csr_wen = 1'b1 ; d_csr_ren = |d_rd; d_csr_wtype = CSR_WTYPE_W; end else begin d_invalid_32bit = 1'b1; end
RV_CSRRS: if (HAVE_CSR) begin d_imm = d_imm_i; d_csr_wen = |d_rs1; d_csr_ren = 1'b1 ; d_csr_wtype = CSR_WTYPE_S; end else begin d_invalid_32bit = 1'b1; end
RV_CSRRC: if (HAVE_CSR) begin d_imm = d_imm_i; d_csr_wen = |d_rs1; d_csr_ren = 1'b1 ; d_csr_wtype = CSR_WTYPE_C; end else begin d_invalid_32bit = 1'b1; end

4
hdl/rv_opcodes.vh
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@ -48,8 +48,8 @@ localparam RV_LHU = 32'b?????????????????101?????0000011;
localparam RV_SB = 32'b?????????????????000?????0100011;
localparam RV_SH = 32'b?????????????????001?????0100011;
localparam RV_SW = 32'b?????????????????010?????0100011;
localparam RV_FENCE = 32'b?????????????????000?????0001111;
localparam RV_FENCE_I = 32'b?????????????????001?????0001111;
localparam RV_FENCE = 32'b????????????00000000000000001111;
localparam RV_FENCE_I = 32'b00000000000000000001000000001111;
localparam RV_ECALL = 32'b00000000000000000000000001110011;
localparam RV_EBREAK = 32'b00000000000100000000000001110011;
localparam RV_CSRRW = 32'b?????????????????001?????1110011;