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Wire privilege through from core to bus masters. Tied off inside core.

This commit is contained in:
Luke Wren 2022-05-24 14:05:26 +01:00
parent c0b5d73cbd
commit 2df1179994
3 changed files with 43 additions and 12 deletions
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7
hdl/hazard3_core.v
View File

@ -25,8 +25,9 @@ module hazard3_core #(
input wire bus_dph_ready_i,
input wire bus_dph_err_i,
output wire [2:0] bus_hsize_i,
output wire [W_ADDR-1:0] bus_haddr_i,
output wire [2:0] bus_hsize_i,
output wire bus_priv_i,
input wire [W_DATA-1:0] bus_rdata_i,
// Load/store port
@ -39,6 +40,7 @@ module hazard3_core #(
output reg [W_ADDR-1:0] bus_haddr_d,
output reg [2:0] bus_hsize_d,
output reg bus_priv_d,
output reg bus_hwrite_d,
output reg [W_DATA-1:0] bus_wdata_d,
input wire [W_DATA-1:0] bus_rdata_d,
@ -79,6 +81,9 @@ wire debug_mode;
assign dbg_halted = DEBUG_SUPPORT && debug_mode;
assign dbg_running = DEBUG_SUPPORT && !debug_mode;
assign bus_priv_i = 1'b1;
always @ (*) bus_priv_d = 1'b1;
// ----------------------------------------------------------------------------
// Pipe Stage F

26
hdl/hazard3_cpu_1port.v
View File

@ -68,8 +68,9 @@ wire core_aph_ready_i;
wire core_dph_ready_i;
wire core_dph_err_i;
wire [2:0] core_hsize_i;
wire [W_ADDR-1:0] core_haddr_i;
wire [2:0] core_hsize_i;
wire core_priv_i;
wire [W_DATA-1:0] core_rdata_i;
@ -83,6 +84,7 @@ wire core_dph_exokay_d;
wire [W_ADDR-1:0] core_haddr_d;
wire [2:0] core_hsize_d;
wire core_priv_d;
wire core_hwrite_d;
wire [W_DATA-1:0] core_wdata_d;
wire [W_DATA-1:0] core_rdata_d;
@ -103,8 +105,9 @@ hazard3_core #(
.bus_aph_ready_i (core_aph_ready_i),
.bus_dph_ready_i (core_dph_ready_i),
.bus_dph_err_i (core_dph_err_i),
.bus_hsize_i (core_hsize_i),
.bus_haddr_i (core_haddr_i),
.bus_hsize_i (core_hsize_i),
.bus_priv_i (core_priv_i),
.bus_rdata_i (core_rdata_i),
.bus_aph_req_d (core_aph_req_d),
@ -115,6 +118,7 @@ hazard3_core #(
.bus_dph_exokay_d (core_dph_exokay_d),
.bus_haddr_d (core_haddr_d),
.bus_hsize_d (core_hsize_d),
.bus_priv_d (core_priv_d),
.bus_hwrite_d (core_hwrite_d),
.bus_wdata_d (core_wdata_d),
.bus_rdata_d (core_rdata_d),
@ -184,9 +188,17 @@ end
localparam HTRANS_IDLE = 2'b00;
localparam HTRANS_NSEQ = 2'b10;
// Noncacheable nonbufferable privileged data/instr:
localparam HPROT_DATA = 4'b0011;
localparam HPROT_INSTR = 4'b0010;
wire [3:0] hprot_data = {
2'b00, // Noncacheable/nonbufferable
core_priv_d, // Privileged or Normal as per core state
1'b1 // Data access
};
wire [3:0] hprot_instr = {
2'b00, // Noncacheable/nonbufferable
core_priv_i, // Privileged or Normal as per core state
1'b0 // Instruction access
};
assign ahblm_hburst = 3'b000; // HBURST_SINGLE
assign ahblm_hmastlock = 1'b0;
@ -198,14 +210,14 @@ always @ (*) begin
ahblm_haddr = core_haddr_d;
ahblm_hsize = core_hsize_d;
ahblm_hwrite = core_hwrite_d;
ahblm_hprot = HPROT_DATA;
ahblm_hprot = hprot_data;
end else if (bus_gnt_i) begin
ahblm_htrans = HTRANS_NSEQ;
ahblm_hexcl = 1'b0;
ahblm_haddr = core_haddr_i;
ahblm_hsize = core_hsize_i;
ahblm_hwrite = 1'b0;
ahblm_hprot = HPROT_INSTR;
ahblm_hprot = hprot_instr;
end else begin
ahblm_htrans = HTRANS_IDLE;
ahblm_hexcl = 1'b0;

22
hdl/hazard3_cpu_2port.v
View File

@ -81,8 +81,9 @@ wire core_aph_ready_i;
wire core_dph_ready_i;
wire core_dph_err_i;
wire [2:0] core_hsize_i;
wire [W_ADDR-1:0] core_haddr_i;
wire [2:0] core_hsize_i;
wire core_priv_i;
wire [W_DATA-1:0] core_rdata_i;
@ -96,6 +97,7 @@ wire core_dph_exokay_d;
wire [W_ADDR-1:0] core_haddr_d;
wire [2:0] core_hsize_d;
wire core_priv_d;
wire core_hwrite_d;
wire [W_DATA-1:0] core_wdata_d;
wire [W_DATA-1:0] core_rdata_d;
@ -116,8 +118,9 @@ hazard3_core #(
.bus_aph_ready_i (core_aph_ready_i),
.bus_dph_ready_i (core_dph_ready_i),
.bus_dph_err_i (core_dph_err_i),
.bus_hsize_i (core_hsize_i),
.bus_haddr_i (core_haddr_i),
.bus_hsize_i (core_hsize_i),
.bus_priv_i (core_priv_i),
.bus_rdata_i (core_rdata_i),
.bus_aph_req_d (core_aph_req_d),
@ -128,6 +131,7 @@ hazard3_core #(
.bus_dph_exokay_d (core_dph_exokay_d),
.bus_haddr_d (core_haddr_d),
.bus_hsize_d (core_hsize_d),
.bus_priv_d (core_priv_d),
.bus_hwrite_d (core_hwrite_d),
.bus_wdata_d (core_wdata_d),
.bus_rdata_d (core_rdata_d),
@ -176,10 +180,15 @@ assign core_rdata_i = i_hrdata;
assign i_hwrite = 1'b0;
assign i_hburst = 3'h0;
assign i_hprot = 4'b0010;
assign i_hmastlock = 1'b0;
assign i_hwdata = {W_DATA{1'b0}};
assign i_hprot = {
2'b00, // Noncacheable/nonbufferable
core_priv_i, // Privileged or Normal as per core state
1'b0 // Instruction access
};
// ----------------------------------------------------------------------------
// Load/store port
@ -208,9 +217,14 @@ assign core_rdata_d = d_hrdata;
assign d_hwdata = core_wdata_d;
assign d_hburst = 3'h0;
assign d_hprot = 4'b0010;
assign d_hmastlock = 1'b0;
assign d_hprot = {
2'b00, // Noncacheable/nonbufferable
core_priv_d, // Privileged or Normal as per core state
1'b1 // Data access
};
endmodule
`default_nettype wire