From 31efd0704298d37b6b16fed62e7fe8fe012f1a22 Mon Sep 17 00:00:00 2001 From: Luke Wren Date: Sat, 25 Jun 2022 11:32:56 +0100 Subject: [PATCH] Fix incorrect tracking of predictedness of fetch data phase. Fixes performance regression in RV32IMC CoreMark (now runs faster, as it should.) --- hdl/hazard3_decode.v | 5 ++--- hdl/hazard3_frontend.v | 2 +- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/hdl/hazard3_decode.v b/hdl/hazard3_decode.v index d6e67ca..fc08c43 100644 --- a/hdl/hazard3_decode.v +++ b/hdl/hazard3_decode.v @@ -131,9 +131,8 @@ assign d_pc = pc; // Frontend should mark the whole instruction, and nothing but the // instruction, as a predicted branch. This goes wrong when we execute the // address containing the predicted branch twice with different 16-bit -// alignments! We don't care about performance in this case(it took BMC to -// find it), but need to issue a branch-to-self to get back on a linear path, -// otherwise PC and CIR will diverge and we will misexecute. +// alignments (!). We need to issue a branch-to-self to get back on a linear +// path, otherwise PC and CIR will diverge and we will misexecute. wire partial_predicted_branch = !d_starved && |BRANCH_PREDICTOR && d_instr_is_32bit && ^fd_cir_predbranch; diff --git a/hdl/hazard3_frontend.v b/hdl/hazard3_frontend.v index 044a7a1..10d97c8 100644 --- a/hdl/hazard3_frontend.v +++ b/hdl/hazard3_frontend.v @@ -386,7 +386,7 @@ always @ (posedge clk or negedge rst_n) begin }; end mem_data_predbranch <= - |BRANCH_PREDICTOR && btb_match_current_addr ? ( + |BRANCH_PREDICTOR && btb_match_word ? ( btb_src_addr[1] ? 2'b10 : btb_src_size ? 2'b11 : 2'b01 ) :