Sketch in an AMO ALU
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* DO WHAT THE FUCK YOU WANT TO AND DON'T BLAME US PUBLIC LICENSE *
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* Version 3, April 2008 *
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* *
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* Copyright (C) 2018 Luke Wren *
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* Copyright (C) 2021 Luke Wren *
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* *
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* Everyone is permitted to copy and distribute verbatim or modified *
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* copies of this license document and accompanying software, and *
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/**********************************************************************
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* DO WHAT THE FUCK YOU WANT TO AND DON'T BLAME US PUBLIC LICENSE *
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* Version 3, April 2008 *
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* *
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* Copyright (C) 2021 Luke Wren *
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* *
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* Everyone is permitted to copy and distribute verbatim or modified *
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* copies of this license document and accompanying software, and *
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* changing either is allowed. *
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* *
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* TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION *
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* *
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* 0. You just DO WHAT THE FUCK YOU WANT TO. *
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* 1. We're NOT RESPONSIBLE WHEN IT DOESN'T FUCKING WORK. *
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* *
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*********************************************************************/
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// Separate ALU for atomic memory operations
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`default_nettype none
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module hazard3_amo_alu #(
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`include "hazard3_config.vh"
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,
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`include "hazard3_width_const.vh"
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) (
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input wire [W_MEMOP-1:0] op,
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input wire [W_DATA-1:0] op_rs1, // From load
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input wire [W_DATA-1:0] op_rs2, // From core
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output reg [W_DATA-1:0] result
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);
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wire sub = op != MEMOP_AMOADD_W;
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wire cmp_unsigned = op == MEMOP_AMOMINU_W || op == MEMOP_AMOMAXU_W;
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wire [W_DATA-1:0] sum = op_rs1 + (op_rs2 ^ {W_DATA{sub}}) + sub;
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wire rs1_lessthan_rs2 =
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op_rs1[W_DATA-1] == op_rs2[W_DATA-1] ? sum[W_DATA-1] :
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cmp_unsigned ? op_rs2[W_DATA-1] :
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op_rs1[W_DATA-1] ;
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always @ (*) begin
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case(op)
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MEMOP_AMOADD_W : result = sum;
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MEMOP_AMOXOR_W : result = op_rs1 ^ op_rs2;
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MEMOP_AMOAND_W : result = op_rs1 & op_rs2;
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MEMOP_AMOOR_W : result = op_rs1 | op_rs2;
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MEMOP_AMOMIN_W : result = rs1_lessthan_rs2 ? op_rs1 : op_rs2;
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MEMOP_AMOMAX_W : result = rs1_lessthan_rs2 ? op_rs2 : op_rs1;
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MEMOP_AMOMINU_W: result = rs1_lessthan_rs2 ? op_rs1 : op_rs2;
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MEMOP_AMOMAXU_W: result = rs1_lessthan_rs2 ? op_rs2 : op_rs1;
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// AMOSWAP
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default: result = op_rs2;
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endcase
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end
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endmodule
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`default_nettype wire
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