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Stronger property for correct predecode

This commit is contained in:
Luke Wren 2022-04-05 08:14:49 +01:00
parent 20cf408632
commit 35651f52a7
2 changed files with 19 additions and 15 deletions
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12
hdl/hazard3_core.v
View File

@ -82,7 +82,6 @@ assign dbg_running = DEBUG_SUPPORT && !debug_mode;
// ---------------------------------------------------------------------------- // ----------------------------------------------------------------------------
// Pipe Stage F // Pipe Stage F
wire f_jump_req; wire f_jump_req;
wire [W_ADDR-1:0] f_jump_target; wire [W_ADDR-1:0] f_jump_target;
wire f_jump_rdy; wire f_jump_rdy;
@ -366,14 +365,18 @@ always @ (posedge clk or negedge rst_n) begin
end end
`ifdef FORMAL `ifdef FORMAL
always @ (posedge clk) begin always @ (posedge clk) if (rst_n && !x_stall) begin
if (rst_n && !x_stall) begin // If stage 2 sees a reg operand, it must have been correctly predecoded too.
if (|d_rs1)
assert(d_rs1_predecoded == d_rs1);
if (|d_rs2)
assert(d_rs2_predecoded == d_rs2);
// If no reg was predecoded, stage 2 decode must agree there is no reg operand.
if (~|d_rs1_predecoded) if (~|d_rs1_predecoded)
assert(~|d_rs1); assert(~|d_rs1);
if (~|d_rs2_predecoded) if (~|d_rs2_predecoded)
assert(~|d_rs2); assert(~|d_rs2);
end end
end
`endif `endif
always @ (*) begin always @ (*) begin
@ -865,6 +868,7 @@ assign x_jump_req = !x_stall_on_raw && (
d_branchcond == BCOND_ZERO && !x_branch_cmp || d_branchcond == BCOND_ZERO && !x_branch_cmp ||
d_branchcond == BCOND_NZERO && x_branch_cmp d_branchcond == BCOND_NZERO && x_branch_cmp
); );
// ---------------------------------------------------------------------------- // ----------------------------------------------------------------------------
// Pipe Stage M // Pipe Stage M

6
hdl/hazard3_frontend.v
View File

@ -53,11 +53,11 @@ module hazard3_frontend #(
// Provide the rs1/rs2 register numbers which will be in CIR next cycle. // Provide the rs1/rs2 register numbers which will be in CIR next cycle.
// Coarse: valid if this instruction has a nonzero register operand. // Coarse: valid if this instruction has a nonzero register operand.
// (suitable for regfile read) // (Suitable for regfile read)
output reg [4:0] predecode_rs1_coarse, output reg [4:0] predecode_rs1_coarse,
output reg [4:0] predecode_rs2_coarse, output reg [4:0] predecode_rs2_coarse,
// Fine: same as coarse, but more accurate zeroing when e.g. the operand is implicit. // Fine: like coarse, but accurate zeroing when the operand is implicit.
// (suitable for bypass) // (Suitable for bypass. Still not precise enough for stall logic.)
output reg [4:0] predecode_rs1_fine, output reg [4:0] predecode_rs1_fine,
output reg [4:0] predecode_rs2_fine, output reg [4:0] predecode_rs2_fine,