From 357efac66e900651293aaf9d23d8f147bee71e98 Mon Sep 17 00:00:00 2001 From: Luke Wren Date: Mon, 4 Apr 2022 17:58:37 +0100 Subject: [PATCH] Don't decode unnecessary bits in register predecode logic --- hdl/hazard3_frontend.v | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/hdl/hazard3_frontend.v b/hdl/hazard3_frontend.v index 6ce2f17..b206305 100644 --- a/hdl/hazard3_frontend.v +++ b/hdl/hazard3_frontend.v @@ -389,11 +389,9 @@ wire next_instr_is_32bit = next_instr[1:0] == 2'b11; assign next_regs_rs1 = next_instr_is_32bit ? next_instr[19:15] : // 32-bit R, S, B formats - next_instr[1:0] == 2'b00 && next_instr[15:13] == 3'b000 ? 5'd2 : // c.addi4spn - next_instr[1:0] == 2'b01 && next_instr[15:13] == 3'b011 ? 5'd2 : // c.addi16sp - next_instr[1:0] == 2'b10 && next_instr[15:13] == 3'b010 ? 5'd2 : // c.lwsp - next_instr[1:0] == 2'b10 && next_instr[15:13] == 3'b110 ? 5'd2 : // c.swsp - next_instr[1:0] == 2'b01 && next_instr[15:13] == 3'b000 ? next_instr[11:7] : // c.addi + next_instr[1:0] == 2'b00 && next_instr[14:13] == 2'b00 ? 5'd2 : // c.addi4spn + don't care + next_instr[1:0] == 2'b01 && next_instr[15 ] == 1'b0 ? next_instr[11:7] : // c.addi, c.addi16sp + don't care (jal, li) + next_instr[1:0] == 2'b10 && next_instr[14 ] == 1'b1 ? 5'd2 : // c.lwsp, c.lwsp + don't care next_instr[1:0] == 2'b10 ? next_instr[11:7] : {2'b01, next_instr[9:7]};