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Fix acmd FSM not selecting the correct hart signal for its state transitions, and make flush take precedence over debug injection in frontend. (Changes from aborted abstract access memory implementation, see abstract-access-memory branch)

This commit is contained in:
Luke Wren 2022-07-02 22:46:20 +01:00
parent edfe7f601e
commit 36cee73d1f
2 changed files with 13 additions and 9 deletions
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12
hdl/debug/dm/hazard3_dm.v
View File

@ -465,7 +465,7 @@ always @ (posedge clk or negedge rst_n) begin
abstractcs_cmderr <= abstractcs_cmderr & ~dmi_pwdata[10:8];
if (abstractcs_cmderr == CMDERR_OK && abstractcs_busy && dmi_access_illegal_when_busy)
abstractcs_cmderr <= CMDERR_BUSY;
if (acmd_state != S_IDLE && hart_instr_caught_exception)
if (acmd_state != S_IDLE && hart_instr_caught_exception[hartsel])
abstractcs_cmderr <= CMDERR_EXCEPTION;
case (acmd_state)
S_IDLE: begin
@ -500,7 +500,7 @@ always @ (posedge clk or negedge rst_n) begin
acmd_state <= S_WAIT_REGEBREAK;
end
S_WAIT_REGEBREAK: begin
if (hart_instr_caught_ebreak) begin
if (hart_instr_caught_ebreak[hartsel]) begin
if (acmd_prev_postexec)
acmd_state <= S_ISSUE_PROGBUF0;
else
@ -513,21 +513,21 @@ always @ (posedge clk or negedge rst_n) begin
acmd_state <= S_ISSUE_PROGBUF1;
end
S_ISSUE_PROGBUF1: begin
if (hart_instr_caught_exception || hart_instr_caught_ebreak) begin
if (hart_instr_caught_exception[hartsel] || hart_instr_caught_ebreak[hartsel]) begin
acmd_state <= S_IDLE;
end else if (hart_instr_data_rdy[hartsel]) begin
acmd_state <= S_ISSUE_IMPEBREAK;
end
end
S_ISSUE_IMPEBREAK: begin
if (hart_instr_caught_exception || hart_instr_caught_ebreak) begin
if (hart_instr_caught_exception[hartsel] || hart_instr_caught_ebreak[hartsel]) begin
acmd_state <= S_IDLE;
end else if (hart_instr_data_rdy[hartsel]) begin
acmd_state <= S_WAIT_IMPEBREAK;
end
end
S_WAIT_IMPEBREAK: begin
if (hart_instr_caught_exception || hart_instr_caught_ebreak) begin
if (hart_instr_caught_exception[hartsel] || hart_instr_caught_ebreak[hartsel]) begin
acmd_state <= S_IDLE;
end
end
@ -662,4 +662,6 @@ end
endmodule
`ifndef YOSYS
`default_nettype wire
`endif

10
hdl/hazard3_frontend.v
View File

@ -154,14 +154,16 @@ always @ (posedge clk or negedge rst_n) begin: fifo_update
fifo_valid[i] && fifo_pop && fifo_push ? mem_data_hwvld :
!fifo_valid[i] && fifo_valid[i - 1] && fifo_push && !fifo_pop ? mem_data_hwvld : fifo_valid_hw[i];
end
// Allow DM to inject instructions directly into the lowest-numbered queue
// entry. This mux should not extend critical path since it is balanced
// with the instruction-assembly muxes on the queue bypass path.
// Allow DM to inject instructions directly into the lowest-numbered
// queue entry. This mux should not extend critical path since it is
// balanced with the instruction-assembly muxes on the queue bypass
// path. Note that flush takes precedence over debug injection
// (and the debug module design must account for this)
if (fifo_dbg_inject) begin
fifo_mem[0] <= dbg_instr_data;
fifo_err[0] <= 1'b0;
fifo_predbranch[0] <= 2'b00;
fifo_valid_hw[0] <= 2'b11;
fifo_valid_hw[0] <= jump_now ? 2'b00 : 2'b11;
end
`ifdef HAZARD3_ASSERTIONS
// FIFO validity must be compact, so we can always consume from the end