From 3ae843034d14e66d1afc5a6e9dd55f761c7de402 Mon Sep 17 00:00:00 2001 From: Luke Wren Date: Sun, 4 Sep 2022 23:42:48 +0100 Subject: [PATCH] Example soc: connect up power signals and always-on clock. Set more parameters explicitly. --- example_soc/fpga/fpga_icebreaker.v | 33 +++++++++++----- example_soc/soc/example_soc.v | 62 +++++++++++++++++++++--------- 2 files changed, 67 insertions(+), 28 deletions(-) diff --git a/example_soc/fpga/fpga_icebreaker.v b/example_soc/fpga/fpga_icebreaker.v index 12b7da7..c5493a7 100644 --- a/example_soc/fpga/fpga_icebreaker.v +++ b/example_soc/fpga/fpga_icebreaker.v @@ -62,16 +62,29 @@ activity_led #( ); example_soc #( - .EXTENSION_A (1), - .EXTENSION_C (0), - .EXTENSION_M (1), - .MUL_FAST (0), - .MULH_FAST (0), - .EXTENSION_ZBA (0), - .EXTENSION_ZBB (0), - .EXTENSION_ZBC (0), - .EXTENSION_ZBS (0), - .CSR_COUNTER (0) + .EXTENSION_A (1), + .EXTENSION_C (0), + .EXTENSION_M (1), + .EXTENSION_ZBA (0), + .EXTENSION_ZBB (0), + .EXTENSION_ZBC (0), + .EXTENSION_ZBS (0), + .EXTENSION_ZBKB (0), + .EXTENSION_ZIFENCEI (0), + .EXTENSION_XH3BEXTM (0), + .EXTENSION_XH3POWER (0), + .CSR_COUNTER (0), + .U_MODE (0), + .PMP_REGIONS (0), + .BREAKPOINT_TRIGGERS (0), + .IRQ_PRIORITY_BITS (0), + .REDUCED_BYPASS (0), + .MULDIV_UNROLL (1), + .MUL_FAST (0), + .MUL_FASTER (0), + .MULH_FAST (0), + .FAST_BRANCHCMP (1), + .BRANCH_PREDICTOR (0) ) soc_u ( .clk (clk_sys), .rst_n (rst_n_sys), diff --git a/example_soc/soc/example_soc.v b/example_soc/soc/example_soc.v index 1a8a62c..c956479 100644 --- a/example_soc/soc/example_soc.v +++ b/example_soc/soc/example_soc.v @@ -235,12 +235,15 @@ wire proc_hexokay = 1'b1; // No global monitor wire [W_DATA-1:0] proc_hwdata; wire [W_DATA-1:0] proc_hrdata; -wire uart_irq; -wire timer_irq; +wire pwrup_req; +wire unblock_out; + +wire uart_irq; +wire timer_irq; hazard3_cpu_1port #( // These must have the values given here for you to end up with a useful SoC: - .RESET_VECTOR (32'h0000_00c0), + .RESET_VECTOR (32'h0000_0040), .MTVEC_INIT (32'h0000_0000), .CSR_M_MANDATORY (1), .CSR_M_TRAP (1), @@ -249,25 +252,48 @@ hazard3_cpu_1port #( .RESET_REGFILE (0), // Can be overridden from the defaults in hazard3_config.vh during // instantiation of example_soc(): - .EXTENSION_A (EXTENSION_A), - .EXTENSION_C (EXTENSION_C), - .EXTENSION_M (EXTENSION_M), - .EXTENSION_ZBA (EXTENSION_ZBA), - .EXTENSION_ZBB (EXTENSION_ZBB), - .EXTENSION_ZBC (EXTENSION_ZBC), - .EXTENSION_ZBS (EXTENSION_ZBS), - .CSR_COUNTER (CSR_COUNTER), - .MVENDORID_VAL (MVENDORID_VAL), - .MIMPID_VAL (MIMPID_VAL), - .MHARTID_VAL (MHARTID_VAL), - .REDUCED_BYPASS (REDUCED_BYPASS), - .MULDIV_UNROLL (MULDIV_UNROLL), - .MUL_FAST (MUL_FAST), - .MTVEC_WMASK (MTVEC_WMASK) + .EXTENSION_A (EXTENSION_A), + .EXTENSION_C (EXTENSION_C), + .EXTENSION_M (EXTENSION_M), + .EXTENSION_ZBA (EXTENSION_ZBA), + .EXTENSION_ZBB (EXTENSION_ZBB), + .EXTENSION_ZBC (EXTENSION_ZBC), + .EXTENSION_ZBS (EXTENSION_ZBS), + .EXTENSION_ZBKB (EXTENSION_ZBKB), + .EXTENSION_ZIFENCEI (EXTENSION_ZIFENCEI), + .EXTENSION_XH3BEXTM (EXTENSION_XH3BEXTM), + .EXTENSION_XH3POWER (EXTENSION_XH3POWER), + .CSR_COUNTER (CSR_COUNTER), + .U_MODE (U_MODE), + .PMP_REGIONS (PMP_REGIONS), + .PMP_GRAIN (PMP_GRAIN), + .PMP_HARDWIRED (PMP_HARDWIRED), + .PMP_HARDWIRED_ADDR (PMP_HARDWIRED_ADDR), + .PMP_HARDWIRED_CFG (PMP_HARDWIRED_CFG), + .MVENDORID_VAL (MVENDORID_VAL), + .BREAKPOINT_TRIGGERS (BREAKPOINT_TRIGGERS), + .IRQ_PRIORITY_BITS (IRQ_PRIORITY_BITS), + .MIMPID_VAL (MIMPID_VAL), + .MHARTID_VAL (MHARTID_VAL), + .REDUCED_BYPASS (REDUCED_BYPASS), + .MULDIV_UNROLL (MULDIV_UNROLL), + .MUL_FAST (MUL_FAST), + .MUL_FASTER (MUL_FASTER), + .MULH_FAST (MULH_FAST), + .FAST_BRANCHCMP (FAST_BRANCHCMP), + .BRANCH_PREDICTOR (BRANCH_PREDICTOR), + .MTVEC_WMASK (MTVEC_WMASK) ) cpu ( .clk (clk), + .clk_always_on (clk), .rst_n (rst_n_cpu), + .pwrup_req (pwrup_req), + .pwrup_ack (pwrup_req), // Tied back + .clk_en (/* unused */), + .unblock_out (unblock_out), + .unblock_in (unblock_out), // Tied back + .haddr (proc_haddr), .hwrite (proc_hwrite), .htrans (proc_htrans),