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Cleanup some unused signals

This commit is contained in:
Luke Wren 2022-08-20 16:44:39 +01:00
parent 96e55a5446
commit 3b7cd9bc96
5 changed files with 4 additions and 19 deletions
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11
hdl/arith/hazard3_alu.v
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@ -24,13 +24,6 @@ module hazard3_alu #(
// ----------------------------------------------------------------------------
// Fiddle around with add/sub, comparisons etc (all related).
function msb;
input [W_DATA-1:0] x;
begin
msb = x[W_DATA-1];
end
endfunction
wire sub = !(aluop == ALUOP_ADD || (|EXTENSION_ZBA && aluop == ALUOP_SHXADD));
wire inv_op_b = sub && !(
@ -52,8 +45,8 @@ wire cmp_is_unsigned = aluop == ALUOP_LTU ||
|EXTENSION_ZBB && aluop == ALUOP_MAXU ||
|EXTENSION_ZBB && aluop == ALUOP_MINU;
wire lt = msb(op_a) == msb(op_b) ? msb(sum) :
cmp_is_unsigned ? msb(op_b) : msb(op_a) ;
wire lt = op_a[W_DATA-1] == op_b[W_DATA-1] ? sum[W_DATA-1] :
cmp_is_unsigned ? op_b[W_DATA-1] : op_a[W_DATA-1] ;
assign cmp = aluop == ALUOP_SUB ? |op_xor : lt;

3
hdl/hazard3_cpu_2port.v
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@ -87,7 +87,6 @@ module hazard3_cpu_2port #(
// Instruction fetch signals
wire core_aph_req_i;
wire core_aph_panic_i; // unused as there's no arbitration
wire core_aph_ready_i;
wire core_dph_ready_i;
wire core_dph_err_i;
@ -124,7 +123,7 @@ hazard3_core #(
`endif
.bus_aph_req_i (core_aph_req_i),
.bus_aph_panic_i (core_aph_panic_i),
.bus_aph_panic_i (/* unused for 2port */),
.bus_aph_ready_i (core_aph_ready_i),
.bus_dph_ready_i (core_dph_ready_i),
.bus_dph_err_i (core_dph_err_i),

2
hdl/hazard3_csr.v
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@ -277,8 +277,6 @@ always @ (posedge clk or negedge rst_n) begin
end
end
wire mie_meie = mie[11];
// Interrupt pending register (assigned later). In our implementation this
// register is entirely read-only.
wire [XLEN-1:0] mip;

1
hdl/hazard3_frontend.v
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@ -123,6 +123,7 @@ always @ (*) begin: boundary_conditions
integer i;
fifo_mem[FIFO_DEPTH] = mem_data;
fifo_predbranch[FIFO_DEPTH] = 2'b00;
fifo_err[FIFO_DEPTH] = 1'b0;
fifo_valid_hw[FIFO_DEPTH] = 2'b00;
fifo_valid[FIFO_DEPTH] = 1'b0;
fifo_valid[-1] = 1'b1;

6
hdl/hazard3_pmp.v
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@ -183,7 +183,6 @@ end
// load/store/AMO alignment fault (mcause = 4, 6), in the case that both
// happen, and we choose alignment fault in this case.
reg d_match;
reg d_m; // Hazard3 extension (M-mode without locking)
reg d_l;
reg d_r;
@ -191,7 +190,6 @@ reg d_w;
always @ (*) begin: check_d_match
integer i;
d_match = 1'b0;
d_m = 1'b0;
d_l = 1'b0;
d_r = 1'b0;
@ -200,7 +198,6 @@ always @ (*) begin: check_d_match
// inferred as a priority mux structure (cascade mux).
for (i = PMP_REGIONS - 1; i >= 0; i = i - 1) begin
if (|pmpcfg_a[i] && (d_addr & match_mask[i]) == match_addr[i]) begin
d_match = 1'b1;
d_m = pmpcfg_m[i];
d_l = pmpcfg_l[i];
d_r = pmpcfg_r[i];
@ -240,7 +237,6 @@ end
// completely match a lower-numbered region. We don't accumulate the partial
// match across all regions.
reg i_match;
reg i_partial_match;
reg i_m; // Hazard3 extension (M-mode without locking)
reg i_l;
@ -251,7 +247,6 @@ wire [W_ADDR-1:0] i_addr_hw1 = i_addr + 2'h2;
always @ (*) begin: check_i_match
integer i;
reg match_hw0, match_hw1;
i_match = 1'b0;
i_partial_match = 1'b0;
i_m = 1'b0;
i_l = 1'b0;
@ -260,7 +255,6 @@ always @ (*) begin: check_i_match
match_hw0 = |pmpcfg_a[i] && (i_addr & match_mask[i]) == match_addr[i];
match_hw1 = |pmpcfg_a[i] && (i_addr_hw1 & match_mask[i]) == match_addr[i];
if (match_hw0 || match_hw1) begin
i_match = 1'b1;
i_partial_match = (match_hw0 ^ match_hw1) && i_instr_is_32bit;
i_m = pmpcfg_m[i];
i_l = pmpcfg_l[i];