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Remove the halfword fetch thing, was only really useful on RISCBoy

This commit is contained in:
Luke Wren 2022-04-02 10:54:16 +01:00
parent 7b8fe43c1c
commit 3c61fae9ef
2 changed files with 5 additions and 6 deletions
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9
hdl/hazard3_frontend.v
View File

@ -256,19 +256,18 @@ always @ (posedge clk or negedge rst_n)
reg [W_ADDR-1:0] mem_addr_r;
reg mem_addr_vld_r;
reg mem_size_r;
// Downstream accesses are always word-sized word-aligned.
assign mem_addr = mem_addr_r;
assign mem_addr_vld = mem_addr_vld_r && !reset_holdoff;
assign mem_size = mem_size_r;
assign mem_size = 1'b1;
always @ (*) begin
mem_addr_r = {W_ADDR{1'b0}};
mem_addr_vld_r = 1'b1;
mem_size_r = 1'b1; // almost all accesses are 32 bit
case (1'b1)
mem_addr_hold : begin mem_addr_r = {fetch_addr[W_ADDR-1:2], unaligned_jump_aph, 1'b0}; mem_size_r = !unaligned_jump_aph; end
jump_target_vld : begin mem_addr_r = jump_target; mem_size_r = !unaligned_jump_now; end
mem_addr_hold : begin mem_addr_r = fetch_addr; end
jump_target_vld : begin mem_addr_r = {jump_target[W_ADDR-1:2], 2'b00}; end
DEBUG_SUPPORT && debug_mode : begin mem_addr_vld_r = 1'b0; end
!fetch_stall : begin mem_addr_r = fetch_addr; end
default : begin mem_addr_vld_r = 1'b0; end

2
test/sim/riscv-compliance/test.gtkw
View File

@ -2,7 +2,7 @@
[*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI
[*] Sat May 22 08:36:50 2021
[*]
[dumpfile] "/home/luke/proj/hazard3/test/riscv-compliance/tmp/C-cbeqz-01-on-rv32ic.vcd"
[dumpfile] "./tmp/I-beq-01-on-rv32i.vcd"
[dumpfile_mtime] "Sat May 22 08:33:31 2021"
[dumpfile_size] 1008774
[savefile] "/home/luke/proj/hazard3/test/riscv-compliance/test.gtkw"