Document some IRQ CSRs, and instruction timings
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Luke Wren
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*.pdf
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.PHONY: all clean view
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all:
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asciidoctor-pdf hazard3.adoc
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view: all
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xdg-open hazard3.pdf
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clean:
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rm -f hazard3.pdf
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Building
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--------
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```bash
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# Get tools
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sudo apt install ruby-asciidoctor-pdf
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# Build
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make
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```
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:sectnums:
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:toc:
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:toclevels: 3
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:doctype: book
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:times: ×
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= Hazard3
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include::sections/introduction.adoc[]
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include::sections/instruction_timings.adoc[]
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include::sections/csr.adoc[]
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== CSRs
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The RISC-V privileged specification affords flexibility as to which CSRs are implemented, and how they behave. This section documents the concrete behaviour of Hazard3's standard and nonstandard M-mode CSRs, as implemented.
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=== Standard CSRs
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==== mvendorid
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Address: `0xf11`
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Read-only, constant. Value is configured when the processor is instantiated. Should contain either all-zeroes, or a valid JEDEC JEP106 vendor ID.
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==== marchid
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Address: `0xf12`
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Read-only, constant. Architecture identifier for Hazard3, value can be altered when the processor is instantiated. Default is currently all zeroes as unregistered.
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==== mimpid
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Address: `0xf12`
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Read-only, constant. Value is configured when the processor is instantiated. Should contain either all-zeroes, or some number specifiying a version of Hazard3 (e.g. git hash).
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==== mstatus
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blah blah
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==== misa
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Read-only, constant. Value depends on which ISA extensions Hazard5 is configured with.
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=== Custom CSRs
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These are all allocated in the space `0xbc0` through `0xbff` which is available for custom read/write M-mode CSRs, and `0xfc0` through `0xfff` which is available for custom read-only M-mode CSRs.
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==== midcr
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Address: `0xbc0`
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Implementation-defined control register. Miscellaneous nonstandard controls.
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[cols="10h,20h,~", options="header"]
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|===
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| Bits | Name | Description
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| 31:1 | - | RES0
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| 0 | `eivect` | Modified external interrupt vectoring. If 0, use standard behaviour: all external interrupts set interrupt `mcause` of 11 and vector to `mtvec + 0x2c`. If 1, external interrupts use distinct interrupt `mcause` numbers 16 upward, and distinct vectors `mtvec + (irq + 16) * 4`. Resets to 0. Has no effect when `mtvec[0]` is 0.
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|===
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==== meie0
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Address: `0xbe0`
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External interrupt enable register 0. Contains a read-write bit for each external interrupt request IRQ0 through IRQ31. A `1` bit indicates that interrupt is currently enabled.
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Addresses `0xbe1` through `0xbe3` are reserved for further `meie` registers, supporting up to 128 external interrupts.
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An external interrupt is taken when all of the following are true:
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* The interrupt is currently asserted in `meip0`
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* The matching interrupt enable bit is set in `meie0`
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* The standard M-mode interrupt enable `mstatus.mie` is set
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* The standard M-mode global external interrupt enable `mie.meie` is set
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`meie0` resets to *all-ones*, for compatibility with software which is only aware of `mstatus` and `mie`. Because `mstatus.mie` and `mie.meie` are both initially clear, the core will not take interrupts straight out of reset, but it is strongly recommended to configure `meie0` before setting the global interrupt enable, to avoid interrupts from unexpected sources.
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==== meip0
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Address: `0xfe0`
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External IRQ pending register 0. Contains a read-only bit for each external interrupt request IRQ0 through IRQ31. A `1` bit indicates that interrupt is currently asserted. IRQs are assumed to be level-sensitive, and the relevant `meip0` bit is cleared by servicing the requestor so that it deasserts its interrupt request.
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Addresses `0xfe1` through `0xfe3` are reserved for further `meip` registers, supporting up to 128 external interrupts.
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When any bit is set in `meip0`, the standard external interrupt pending bit `mip.meip` is also set. An external interrupt is taken when all of the following are true:
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* The interrupt is currently asserted in `meip0`
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* The matching interrupt enable bit is set in `meie0`
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* The standard M-mode interrupt enable `mstatus.mie` is set
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* The standard M-mode global external interrupt enable `mie.meie` is set
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In this case, the processor jumps to either:
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* `mtvec` directly, if vectoring is disabled (`mtvec[0]` is 0)
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* `mtvec + 0x2c`, if vectoring is enabled (`mtvec[0]` is 1) and modified external IRQ vectoring is disabled (`midcr.eivect` is 0)
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* `mtvect + (mlei + 16) * 4`, if vectoring is enabled (`mtvec[0]` is 1) and modified external IRQ vectoring is enabled (`midcr.eivect` is 1). `
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** `mlei` is a read-only CSR containing the lowest-numbered
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==== mlei
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Address: `0xfe4`
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Lowest external interrupt. Contains the index of the lowest-numbered external interrupt which is both asserted in `meip0` and enabled in `meie0`. Can be used for faster software vectoring when modified external interrupt vectoring (`midcr.eivect = 1`) is not in use.
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[cols="10h,20h,~", options="header"]
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|===
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| Bits | Name | Description
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| 31:5 | - | RES0
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| 4:0 | - | Index of the lowest-numbered active external interrupt. A LSB-first priority encode of `meip0 & meie0`. Zero when no external interrupts are both pending and enabled.
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|===
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==== Maybe-adds
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An option to clear a bit in `meie0` when that interrupt is taken, and set it when an `mret` has a matching `mcause` for that interrupt. Makes preemption support easier.
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== Instruction Cycle Counts
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All timings are given assuming perfect bus behaviour (no stalls). Stalling of the `I` bus can delay execution indefinitely, as can stalling of the `D` bus during a load or store.
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=== RV32I
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[%autowidth.stretch, options="header"]
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|===
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| Instruction | Cycles | Note
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3+| Integer Register-register
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| `add rd, rs1, rs2` | 1 |
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| `sub rd, rs1, rs2` | 1 |
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| `slt rd, rs1, rs2` | 1 |
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| `sltu rd, rs1, rs2` | 1 |
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| `and rd, rs1, rs2` | 1 |
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| `or rd, rs1, rs2` | 1 |
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| `xor rd, rs1, rs2` | 1 |
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| `sll rd, rs1, rs2` | 1 |
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| `srl rd, rs1, rs2` | 1 |
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| `sra rd, rs1, rs2` | 1 |
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3+| Integer Register-immediate
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| `addi rd, rs1, imm` | 1 | `nop` is a pseudo-op for `addi x0, x0, 0`
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| `slti rd, rs1, imm` | 1 |
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| `sltiu rd, rs1, imm` | 1 |
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| `andi rd, rs1, imm` | 1 |
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| `ori rd, rs1, imm` | 1 |
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| `xori rd, rs1, imm` | 1 |
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| `slli rd, rs1, imm` | 1 |
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| `srli rd, rs1, imm` | 1 |
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| `srai rd, rs1, imm` | 1 |
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3+| Large Immediate
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| `lui rd, imm` | 1 |
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| `auipc rd, imm` | 1 |
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3+| Control Transfer
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| `jal rd, label` | 2footnote:unaligned_branch[A branch to a 32-bit instruction which is not 32-bit-aligned requires one additional cycle, because two naturally-aligned bus cycles are required to fetch the target instruction.]|
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| `jalr rd, rs1, imm` | 2footnote:unaligned_branch[] |
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| `beq rs1, rs2, label`| 1 or 2footnote:unaligned_branch[] | 1 if nontaken, 2 if taken.
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| `bne rs1, rs2, label`| 1 or 2footnote:unaligned_branch[] | 1 if nontaken, 2 if taken.
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| `blt rs1, rs2, label`| 1 or 2footnote:unaligned_branch[] | 1 if nontaken, 2 if taken.
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| `bge rs1, rs2, label`| 1 or 2footnote:unaligned_branch[] | 1 if nontaken, 2 if taken.
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| `bltu rs1, rs2, label`| 1 or 2footnote:unaligned_branch[] | 1 if nontaken, 2 if taken.
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| `bgeu rs1, rs2, label`| 1 or 2footnote:unaligned_branch[] | 1 if nontaken, 2 if taken.
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3+| Load and Store
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| `lw rd, imm(rs1)` | 1 or 2 | 1 if next instruction is independent, 2 if dependent.footnote:data_dependency[If an instruction uses load data (from stage 3) in stage 2, a 1-cycle bubble is inserted after the load. Load-data to store-data dependency does not experience this, because the store data is used in stage 3. However, load-data to store-address (or e.g. load-to-add) does qualify.]
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| `lh rd, imm(rs1)` | 1 or 2 | 1 if next instruction is independent, 2 if dependent.footnote:data_dependency[]
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| `lhu rd, imm(rs1)` | 1 or 2 | 1 if next instruction is independent, 2 if dependent.footnote:data_dependency[]
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| `lb rd, imm(rs1)` | 1 or 2 | 1 if next instruction is independent, 2 if dependent.footnote:data_dependency[]
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| `lbu rd, imm(rs1)` | 1 or 2 | 1 if next instruction is independent, 2 if dependent.footnote:data_dependency[]
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| `sw rs2, imm(rs1)` | 1 |
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| `sh rs2, imm(rs1)` | 1 |
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| `sb rs2, imm(rs1)` | 1 |
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|===
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=== M Extension
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Timings assume the core is configured with `MULDIV_UNROLL = 2` and `MUL_FAST = 1`. I.e. the sequential multiply/divide circuit processes two bits per cycle, and a separate dedicated multiplier is present for the `mul` instruction.
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[%autowidth.stretch, options="header"]
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|===
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| Instruction | Cycles | Note
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3+| 32 {times} 32 -> 32 Multiply
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| `mul rd, rs1, rs2` | 1 or 2 | 1 if next instruction is independent, 2 if dependent.
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3+| 32 {times} 32 -> 64 Multiply, Upper Half
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| `mulh rd, rs1, rs2` | 18 to 20 | Depending on sign correction
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| `mulhsu rd, rs1, rs2` | 18 to 20 | Depending on sign correction
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| `mulhu rd, rs1, rs2` | 18 |
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3+| Divide and Remainder
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| `div` | 18 or 19 | Depending on sign correction
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| `divu` | 18 |
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| `rem` | 18 or 19 | Depending on sign correction
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| `remu` | 18 |
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|===
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=== C Extension
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All C extension 16-bit instructions on Hazard3 are aliases of base RV32I instructions. They perform identically to their 32-bit counterparts.
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A consequence of the C extension is that 32-bit instructions can be non-naturally-aligned. This has no penalty during sequential execution, but branching to a 32-bit instruction that is not 32-bit-aligned carries a 1 cycle penalty, because the instruction fetch is cracked into two naturally-aligned bus accesses.
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=== Privileged Instructions (including Zicsr)
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[%autowidth.stretch, options="header"]
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|===
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| Instruction | Cycles | Note
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3+| CSR Access
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| `csrrw rd, csr, rs1` | 1 |
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| `csrrc rd, csr, rs1` | 1 |
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| `csrrs rd, csr, rs1` | 1 |
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| `csrrwi rd, csr, imm` | 1 |
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| `csrrci rd, csr, imm` | 1 |
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| `csrrsi rd, csr, imm` | 1 |
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3+| Trap Request
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| `ecall` | 3 | Time given is for jumping to `mtvec`
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| `ebreak` | 3 | Time given is for jumping to `mtvec`
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|===
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== Introduction
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Hazard3 is a 3-stage RISC-V processor, providing the following architectural support:
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* `RV32I`: 32-bit base instruction set
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* `M` extension: integer multiply/divide/modulo
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* `C` extension: compressed instructions
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* `Zicsr` extension: CSR access
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* M-mode privileged instructions `ECALL`, `EBREAK`, `MRET`
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* The machine-mode (M-mode) privilege state, and standard M-mode CSRs
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The following are planned for future implementation:
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* Support for `WFI` instruction
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* Debug support
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* `A` extension: atomic memory access
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** `LR`/`SC` fully supported
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** AMONone PMA on all of memory (AMOs are decoded but unconditionally trigger access fault without attempting memory access)
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* Some nonstandard M-mode CSRs for interrupt control etc
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