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(reg-meicontext) /Subtype /Link @@ -86217,7 +86352,7 @@ endobj /Type /Annot >> endobj -676 0 obj +677 0 obj << /Border [0 0 0] /Dest (reg-meicontext) /Subtype /Link @@ -86225,7 +86360,7 @@ endobj /Type /Annot >> endobj -677 0 obj +678 0 obj << /Border [0 0 0] /Dest (_custom_memory_protection_csrs) /Subtype /Link @@ -86233,7 +86368,7 @@ endobj /Type /Annot >> endobj -678 0 obj +679 0 obj << /Border [0 0 0] /Dest (_custom_memory_protection_csrs) /Subtype /Link @@ -86241,7 +86376,7 @@ endobj /Type /Annot >> endobj -679 0 obj +680 0 obj << /Border [0 0 0] /Dest (reg-pmpcfgm0) /Subtype /Link @@ -86249,7 +86384,7 @@ endobj /Type /Annot >> endobj -680 0 obj +681 0 obj << /Border [0 0 0] /Dest (reg-pmpcfgm0) /Subtype /Link @@ -86257,7 +86392,7 @@ endobj /Type /Annot >> endobj -681 0 obj +682 0 obj << /Border [0 0 0] /Dest (_custom_power_control_csrs) /Subtype /Link @@ -86265,7 +86400,7 @@ endobj /Type /Annot >> endobj -682 0 obj +683 0 obj << /Border [0 0 0] /Dest (_custom_power_control_csrs) /Subtype /Link @@ -86273,7 +86408,7 @@ endobj /Type /Annot >> endobj -683 0 obj +684 0 obj << /Border [0 0 0] /Dest (reg-msleep) /Subtype /Link @@ -86281,7 +86416,7 @@ endobj /Type /Annot >> endobj -684 0 obj +685 0 obj << /Border [0 0 0] /Dest (reg-msleep) /Subtype /Link @@ -86289,7 +86424,7 @@ endobj /Type /Annot >> endobj -685 0 obj +686 0 obj << /Border [0 0 0] /Dest (_custom_extensions) /Subtype /Link @@ -86297,7 +86432,7 @@ endobj /Type /Annot >> endobj -686 0 obj +687 0 obj << /Border [0 0 0] /Dest (_custom_extensions) /Subtype /Link @@ -86305,7 +86440,7 @@ endobj /Type /Annot >> endobj -687 0 obj +688 0 obj << /Border [0 0 0] /Dest (extension-xh3irq-section) /Subtype /Link @@ -86313,7 +86448,7 @@ endobj /Type /Annot >> endobj -688 0 obj +689 0 obj << /Border [0 0 0] /Dest (extension-xh3irq-section) /Subtype /Link @@ -86321,7 +86456,7 @@ endobj /Type /Annot >> endobj -689 0 obj +690 0 obj << /Border [0 0 0] /Dest (extension-xh3pmpm-section) /Subtype /Link @@ -86329,7 +86464,7 @@ endobj /Type /Annot >> endobj -690 0 obj +691 0 obj << /Border [0 0 0] /Dest (extension-xh3pmpm-section) /Subtype /Link @@ -86337,7 +86472,7 @@ endobj /Type /Annot >> endobj -691 0 obj +692 0 obj << /Border [0 0 0] /Dest (extension-xh3power-section) /Subtype /Link @@ -86345,7 +86480,7 @@ endobj /Type /Annot >> endobj -692 0 obj +693 0 obj << /Border [0 0 0] /Dest (extension-xh3power-section) /Subtype /Link @@ -86353,7 +86488,7 @@ endobj /Type /Annot >> endobj -693 0 obj +694 0 obj << /Border [0 0 0] /Dest (_h3_block) /Subtype /Link @@ -86361,7 +86496,7 @@ endobj /Type /Annot >> endobj -694 0 obj +695 0 obj << /Border [0 0 0] /Dest (_h3_block) /Subtype /Link @@ -86369,7 +86504,7 @@ endobj /Type /Annot >> endobj -695 0 obj +696 0 obj << /Border [0 0 0] /Dest (_h3_unblock) /Subtype /Link @@ -86377,7 +86512,7 @@ endobj /Type /Annot >> endobj -696 0 obj +697 0 obj << /Border [0 0 0] /Dest (_h3_unblock) /Subtype /Link @@ -86385,7 +86520,7 @@ endobj /Type /Annot >> endobj -697 0 obj +698 0 obj << /Border [0 0 0] /Dest (extension-xh3bextm-section) /Subtype /Link @@ -86393,7 +86528,7 @@ endobj /Type /Annot >> endobj -698 0 obj +699 0 obj << /Border [0 0 0] /Dest (extension-xh3bextm-section) /Subtype /Link @@ -86401,7 +86536,7 @@ endobj /Type /Annot >> endobj -699 0 obj +700 0 obj << /Border [0 0 0] /Dest (_h3_bextm) /Subtype /Link @@ -86409,7 +86544,7 @@ endobj /Type /Annot >> endobj -700 0 obj +701 0 obj << /Border [0 0 0] /Dest (_h3_bextm) /Subtype /Link @@ -86417,7 +86552,7 @@ endobj /Type /Annot >> endobj -701 0 obj +702 0 obj << /Border [0 0 0] /Dest (_h3_bextmi) /Subtype /Link @@ -86425,7 +86560,7 @@ endobj /Type /Annot >> endobj -702 0 obj +703 0 obj << /Border [0 0 0] /Dest (_h3_bextmi) /Subtype /Link @@ -86433,7 +86568,7 @@ endobj /Type /Annot >> endobj -703 0 obj +704 0 obj << /Border [0 0 0] /Dest (debug-chapter) /Subtype /Link @@ -86441,7 +86576,7 @@ endobj /Type /Annot >> endobj -704 0 obj +705 0 obj << /Border [0 0 0] /Dest (debug-chapter) /Subtype /Link @@ -86449,7 +86584,7 @@ endobj /Type /Annot >> endobj -705 0 obj +706 0 obj << /Border [0 0 0] /Dest (_debug_topologies) /Subtype /Link @@ -86457,7 +86592,7 @@ endobj /Type /Annot >> endobj -706 0 obj +707 0 obj << /Border [0 0 0] /Dest (_debug_topologies) /Subtype /Link @@ -86465,7 +86600,7 @@ endobj /Type /Annot >> endobj -707 0 obj +708 0 obj << /Border [0 0 0] /Dest (_implementation_defined_behaviour) /Subtype /Link @@ -86473,7 +86608,7 @@ endobj /Type /Annot >> endobj -708 0 obj +709 0 obj << /Border [0 0 0] /Dest (_implementation_defined_behaviour) /Subtype /Link @@ -86481,7 +86616,7 @@ endobj /Type /Annot >> endobj -709 0 obj +710 0 obj << /Border [0 0 0] /Dest (_debug_module_to_core_interface) /Subtype /Link @@ -86489,7 +86624,7 @@ endobj /Type /Annot >> endobj -710 0 obj +711 0 obj << /Border [0 0 0] /Dest (_debug_module_to_core_interface) /Subtype /Link @@ -86497,7 +86632,7 @@ endobj /Type /Annot >> endobj -711 0 obj +712 0 obj << /Border [0 0 0] /Dest (_instruction_cycle_counts) /Subtype /Link @@ -86505,7 +86640,7 @@ endobj /Type /Annot >> endobj -712 0 obj +713 0 obj << /Border [0 0 0] /Dest (_instruction_cycle_counts) /Subtype /Link @@ -86513,7 +86648,7 @@ endobj /Type /Annot >> endobj -713 0 obj +714 0 obj << /Border [0 0 0] /Dest (_rv32i) /Subtype /Link @@ -86521,7 +86656,7 @@ endobj /Type /Annot >> endobj -714 0 obj +715 0 obj << /Border [0 0 0] /Dest (_rv32i) /Subtype /Link @@ -86529,7 +86664,7 @@ endobj /Type /Annot >> endobj -715 0 obj +716 0 obj << /Border [0 0 0] /Dest (_m_extension) /Subtype /Link @@ -86537,7 +86672,7 @@ endobj /Type /Annot >> endobj -716 0 obj +717 0 obj << /Border [0 0 0] /Dest (_m_extension) /Subtype /Link @@ -86545,7 +86680,7 @@ endobj /Type /Annot >> endobj -717 0 obj +718 0 obj << /Border [0 0 0] /Dest (_a_extension) /Subtype /Link @@ -86553,7 +86688,7 @@ endobj /Type /Annot >> endobj -718 0 obj +719 0 obj << /Border [0 0 0] /Dest (_a_extension) /Subtype /Link @@ -86561,7 +86696,7 @@ endobj /Type /Annot >> endobj -719 0 obj +720 0 obj << /Border [0 0 0] /Dest (_c_extension) /Subtype /Link @@ -86569,7 +86704,7 @@ endobj /Type /Annot >> endobj -720 0 obj +721 0 obj << /Border [0 0 0] /Dest (_c_extension) /Subtype /Link @@ -86577,7 +86712,7 @@ endobj /Type /Annot >> endobj -721 0 obj +722 0 obj << /Border [0 0 0] /Dest (_privileged_instructions_including_zicsr) /Subtype /Link @@ -86585,7 +86720,7 @@ endobj /Type /Annot >> endobj -722 0 obj +723 0 obj << /Border [0 0 0] /Dest (_privileged_instructions_including_zicsr) /Subtype /Link @@ -86593,7 +86728,7 @@ endobj /Type /Annot >> endobj -723 0 obj +724 0 obj << /Border [0 0 0] /Dest (_bit_manipulation) /Subtype /Link @@ -86601,7 +86736,7 @@ endobj /Type /Annot >> endobj -724 0 obj +725 0 obj << /Border [0 0 0] /Dest (_bit_manipulation) /Subtype /Link @@ -86609,7 +86744,7 @@ endobj /Type /Annot >> endobj -725 0 obj +726 0 obj << /Border [0 0 0] /Dest (_branch_predictor) /Subtype /Link @@ -86617,7 +86752,7 @@ endobj /Type /Annot >> endobj -726 0 obj +727 0 obj << /Border [0 0 0] /Dest (_branch_predictor) /Subtype /Link @@ -86625,7 +86760,7 @@ endobj /Type /Annot >> endobj -727 0 obj +728 0 obj << /Border [0 0 0] /Dest (_instruction_pseudocode) /Subtype /Link @@ -86633,7 +86768,7 @@ endobj /Type /Annot >> endobj -728 0 obj +729 0 obj << /Border [0 0 0] /Dest (_instruction_pseudocode) /Subtype /Link @@ -86641,7 +86776,7 @@ endobj /Type /Annot >> endobj -729 0 obj +730 0 obj << /Border [0 0 0] /Dest (_rv32i_register_register) /Subtype /Link @@ -86649,7 +86784,7 @@ endobj /Type /Annot >> endobj -730 0 obj +731 0 obj << /Border [0 0 0] /Dest (_rv32i_register_register) /Subtype /Link @@ -86657,7 +86792,7 @@ endobj /Type /Annot >> endobj -731 0 obj +732 0 obj << /Border [0 0 0] /Dest (_add) /Subtype /Link @@ -86665,7 +86800,7 @@ endobj /Type /Annot >> endobj -732 0 obj +733 0 obj << /Border [0 0 0] /Dest (_add) /Subtype /Link @@ -86673,7 +86808,7 @@ endobj /Type /Annot >> endobj -733 0 obj +734 0 obj << /Border [0 0 0] /Dest (_sub) /Subtype /Link @@ -86681,7 +86816,7 @@ endobj /Type /Annot >> endobj -734 0 obj +735 0 obj << /Border [0 0 0] /Dest (_sub) /Subtype /Link @@ -86689,7 +86824,7 @@ endobj /Type /Annot >> endobj -735 0 obj +736 0 obj << /Border [0 0 0] /Dest (_slt) /Subtype /Link @@ -86697,7 +86832,7 @@ endobj /Type /Annot >> endobj -736 0 obj +737 0 obj << /Border [0 0 0] /Dest (_slt) /Subtype /Link @@ -86705,7 +86840,7 @@ endobj /Type /Annot >> endobj -737 0 obj +738 0 obj << /Border [0 0 0] /Dest (_sltu) /Subtype /Link @@ -86713,7 +86848,7 @@ endobj /Type /Annot >> endobj -738 0 obj +739 0 obj << /Border [0 0 0] /Dest (_sltu) /Subtype /Link @@ -86721,7 +86856,7 @@ endobj /Type /Annot >> endobj -739 0 obj +740 0 obj << /Border [0 0 0] /Dest (_and) /Subtype /Link @@ -86729,7 +86864,7 @@ endobj /Type /Annot >> endobj -740 0 obj +741 0 obj << /Border [0 0 0] /Dest (_and) /Subtype /Link @@ -86737,7 +86872,7 @@ endobj /Type /Annot >> endobj -741 0 obj +742 0 obj << /Border [0 0 0] /Dest (_or) /Subtype /Link @@ -86745,7 +86880,7 @@ endobj /Type /Annot >> endobj -742 0 obj +743 0 obj << /Border [0 0 0] /Dest (_or) /Subtype /Link @@ -86753,7 +86888,7 @@ endobj /Type /Annot >> endobj -743 0 obj +744 0 obj << /Border [0 0 0] /Dest (_xor) /Subtype /Link @@ -86761,7 +86896,7 @@ endobj /Type /Annot >> endobj -744 0 obj +745 0 obj << /Border [0 0 0] /Dest (_xor) /Subtype /Link @@ -86769,7 +86904,7 @@ endobj /Type /Annot >> endobj -745 0 obj +746 0 obj << /Border [0 0 0] /Dest (_sll) /Subtype /Link @@ -86777,7 +86912,7 @@ endobj /Type /Annot >> endobj -746 0 obj +747 0 obj << /Border [0 0 0] /Dest (_sll) /Subtype /Link @@ -86785,7 +86920,7 @@ endobj /Type /Annot >> endobj -747 0 obj +748 0 obj << /Border [0 0 0] /Dest (_srl) /Subtype /Link @@ -86793,7 +86928,7 @@ endobj /Type /Annot >> endobj -748 0 obj +749 0 obj << /Border [0 0 0] /Dest (_srl) /Subtype /Link @@ -86801,7 +86936,7 @@ endobj /Type /Annot >> endobj -749 0 obj +750 0 obj << /Border [0 0 0] /Dest (_sra) /Subtype /Link @@ -86809,7 +86944,7 @@ endobj /Type /Annot >> endobj -750 0 obj +751 0 obj << /Border [0 0 0] /Dest (_sra) /Subtype /Link @@ -86817,7 +86952,7 @@ endobj /Type /Annot >> endobj -751 0 obj +752 0 obj << /Border [0 0 0] /Dest (_rv32i_register_immediate) /Subtype /Link @@ -86825,7 +86960,7 @@ endobj /Type /Annot >> endobj -752 0 obj +753 0 obj << /Border [0 0 0] /Dest (_rv32i_register_immediate) /Subtype /Link @@ -86833,7 +86968,7 @@ endobj /Type /Annot >> endobj -753 0 obj +754 0 obj << /Border [0 0 0] /Dest (_addi) /Subtype /Link @@ -86841,7 +86976,7 @@ endobj /Type /Annot >> endobj -754 0 obj +755 0 obj << /Border [0 0 0] /Dest (_addi) /Subtype /Link @@ -86849,7 +86984,7 @@ endobj /Type /Annot >> endobj -755 0 obj +756 0 obj << /Border [0 0 0] /Dest (_slti) /Subtype /Link @@ -86857,7 +86992,7 @@ endobj /Type /Annot >> endobj -756 0 obj +757 0 obj << /Border [0 0 0] /Dest (_slti) /Subtype /Link @@ -86865,7 +87000,7 @@ endobj /Type /Annot >> endobj -757 0 obj +758 0 obj << /Border [0 0 0] /Dest (_sltiu) /Subtype /Link @@ -86873,7 +87008,7 @@ endobj /Type /Annot >> endobj -758 0 obj +759 0 obj << /Border [0 0 0] /Dest (_sltiu) /Subtype /Link @@ -86881,7 +87016,7 @@ endobj /Type /Annot >> endobj -759 0 obj +760 0 obj << /Border [0 0 0] /Dest (_andi) /Subtype /Link @@ -86889,7 +87024,7 @@ endobj /Type /Annot >> endobj -760 0 obj +761 0 obj << /Border [0 0 0] /Dest (_andi) /Subtype /Link @@ -86897,7 +87032,7 @@ endobj /Type /Annot >> endobj -761 0 obj +762 0 obj << /Border [0 0 0] /Dest (_ori) /Subtype /Link @@ -86905,7 +87040,7 @@ endobj /Type /Annot >> endobj -762 0 obj +763 0 obj << /Border [0 0 0] /Dest (_ori) /Subtype /Link @@ -86913,7 +87048,7 @@ endobj /Type /Annot >> endobj -763 0 obj +764 0 obj << /Border [0 0 0] /Dest (_xori) /Subtype /Link @@ -86921,7 +87056,7 @@ endobj /Type /Annot >> endobj -764 0 obj +765 0 obj << /Border [0 0 0] /Dest (_xori) /Subtype /Link @@ -86929,7 +87064,7 @@ endobj /Type /Annot >> endobj -765 0 obj +766 0 obj << /Border [0 0 0] /Dest (_slli) /Subtype /Link @@ -86937,7 +87072,7 @@ endobj /Type /Annot >> endobj -766 0 obj +767 0 obj << /Border [0 0 0] /Dest (_slli) /Subtype /Link @@ -86945,7 +87080,7 @@ endobj /Type /Annot >> endobj -767 0 obj +768 0 obj << /Border [0 0 0] /Dest (_srli) /Subtype /Link @@ -86953,7 +87088,7 @@ endobj /Type /Annot >> endobj -768 0 obj +769 0 obj << /Border [0 0 0] /Dest (_srli) /Subtype /Link @@ -86961,7 +87096,7 @@ endobj /Type /Annot >> endobj -769 0 obj +770 0 obj << /Border [0 0 0] /Dest (_srai) /Subtype /Link @@ -86969,7 +87104,7 @@ endobj /Type /Annot >> endobj -770 0 obj +771 0 obj << /Border [0 0 0] /Dest (_srai) /Subtype /Link @@ -86977,7 +87112,7 @@ endobj /Type /Annot >> endobj -771 0 obj +772 0 obj << /Border [0 0 0] /Dest (_rv32i_large_immediate) /Subtype /Link @@ -86985,7 +87120,7 @@ endobj /Type /Annot >> endobj -772 0 obj +773 0 obj << /Border [0 0 0] /Dest (_rv32i_large_immediate) /Subtype /Link @@ -86993,7 +87128,7 @@ endobj /Type /Annot >> endobj -773 0 obj +774 0 obj << /Border [0 0 0] /Dest (_lui) /Subtype /Link @@ -87001,7 +87136,7 @@ endobj /Type /Annot >> endobj -774 0 obj +775 0 obj << /Border [0 0 0] /Dest (_lui) /Subtype /Link @@ -87009,7 +87144,7 @@ endobj /Type /Annot >> endobj -775 0 obj +776 0 obj << /Border [0 0 0] /Dest (_auipc) /Subtype /Link @@ -87017,7 +87152,7 @@ endobj /Type /Annot >> endobj -776 0 obj +777 0 obj << /Border [0 0 0] /Dest (_auipc) /Subtype /Link @@ -87025,7 +87160,7 @@ endobj /Type /Annot >> endobj -777 0 obj +778 0 obj << /Border [0 0 0] /Dest (_rv32i_control_transfer) /Subtype /Link @@ -87033,7 +87168,7 @@ endobj /Type /Annot >> endobj -778 0 obj +779 0 obj << /Border [0 0 0] /Dest (_rv32i_control_transfer) /Subtype /Link @@ -87041,7 +87176,7 @@ endobj /Type /Annot >> endobj -779 0 obj +780 0 obj << /Border [0 0 0] /Dest (_jal) /Subtype /Link @@ -87049,7 +87184,7 @@ endobj /Type /Annot >> endobj -780 0 obj +781 0 obj << /Border [0 0 0] /Dest (_jal) /Subtype /Link @@ -87057,7 +87192,7 @@ endobj /Type /Annot >> endobj -781 0 obj +782 0 obj << /Border [0 0 0] /Dest (_jalr) /Subtype /Link @@ -87065,7 +87200,7 @@ endobj /Type /Annot >> endobj -782 0 obj +783 0 obj << /Border [0 0 0] /Dest (_jalr) /Subtype /Link @@ -87073,7 +87208,7 @@ endobj /Type /Annot >> endobj -783 0 obj +784 0 obj << /Border [0 0 0] /Dest (_beq) /Subtype /Link @@ -87081,7 +87216,7 @@ endobj /Type /Annot >> endobj -784 0 obj +785 0 obj << /Border [0 0 0] /Dest (_beq) /Subtype /Link @@ -87089,7 +87224,7 @@ endobj /Type /Annot >> endobj -785 0 obj +786 0 obj << /Border [0 0 0] /Dest (_bne) /Subtype /Link @@ -87097,7 +87232,7 @@ endobj /Type /Annot >> endobj -786 0 obj +787 0 obj << /Border [0 0 0] /Dest (_bne) /Subtype /Link @@ -87105,7 +87240,7 @@ endobj /Type /Annot >> endobj -787 0 obj +788 0 obj << /Border [0 0 0] /Dest (_blt) /Subtype /Link @@ -87113,7 +87248,7 @@ endobj /Type /Annot >> endobj -788 0 obj +789 0 obj << /Border [0 0 0] /Dest (_blt) /Subtype /Link @@ -87121,7 +87256,7 @@ endobj /Type /Annot >> endobj -789 0 obj +790 0 obj << /Border [0 0 0] /Dest (_bge) /Subtype /Link @@ -87129,7 +87264,7 @@ endobj /Type /Annot >> endobj -790 0 obj +791 0 obj << /Border [0 0 0] /Dest (_bge) /Subtype /Link @@ -87137,7 +87272,7 @@ endobj /Type /Annot >> endobj -791 0 obj +792 0 obj << /Border [0 0 0] /Dest (_bltu) /Subtype /Link @@ -87145,7 +87280,7 @@ endobj /Type /Annot >> endobj -792 0 obj +793 0 obj << /Border [0 0 0] /Dest (_bltu) /Subtype /Link @@ -87153,7 +87288,7 @@ endobj /Type /Annot >> endobj -793 0 obj +794 0 obj << /Border [0 0 0] /Dest (_bgeu) /Subtype /Link @@ -87161,7 +87296,7 @@ endobj /Type /Annot >> endobj -794 0 obj +795 0 obj << /Border [0 0 0] /Dest (_bgeu) /Subtype /Link @@ -87169,7 +87304,7 @@ endobj /Type /Annot >> endobj -795 0 obj +796 0 obj << /Border [0 0 0] /Dest (_rv32i_load_and_store) /Subtype /Link @@ -87177,7 +87312,7 @@ endobj /Type /Annot >> endobj -796 0 obj +797 0 obj << /Border [0 0 0] /Dest (_rv32i_load_and_store) /Subtype /Link @@ -87185,7 +87320,7 @@ endobj /Type /Annot >> endobj -797 0 obj +798 0 obj << /Border [0 0 0] /Dest (_lw) /Subtype /Link @@ -87193,7 +87328,7 @@ endobj /Type /Annot >> endobj -798 0 obj +799 0 obj << /Border [0 0 0] /Dest (_lw) /Subtype /Link @@ -87201,7 +87336,7 @@ endobj /Type /Annot >> endobj -799 0 obj +800 0 obj << /Border [0 0 0] /Dest (_lh) /Subtype /Link @@ -87209,7 +87344,7 @@ endobj /Type /Annot >> endobj -800 0 obj +801 0 obj << /Border [0 0 0] /Dest (_lh) /Subtype /Link @@ -87217,7 +87352,7 @@ endobj /Type /Annot >> endobj -801 0 obj +802 0 obj << /Border [0 0 0] /Dest (_lhu) /Subtype /Link @@ -87225,7 +87360,7 @@ endobj /Type /Annot >> endobj -802 0 obj +803 0 obj << /Border [0 0 0] /Dest (_lhu) /Subtype /Link @@ -87233,7 +87368,7 @@ endobj /Type /Annot >> endobj -803 0 obj +804 0 obj << /Border [0 0 0] /Dest (_lb) /Subtype /Link @@ -87241,7 +87376,7 @@ endobj /Type /Annot >> endobj -804 0 obj +805 0 obj << /Border [0 0 0] /Dest (_lb) /Subtype /Link @@ -87249,7 +87384,7 @@ endobj /Type /Annot >> endobj -805 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/Border [0 0 0] /Dest (_m_extension_2) /Subtype /Link @@ -87321,7 +87456,7 @@ endobj /Type /Annot >> endobj -814 0 obj +815 0 obj << /Border [0 0 0] /Dest (_m_extension_2) /Subtype /Link @@ -87329,7 +87464,7 @@ endobj /Type /Annot >> endobj -815 0 obj +816 0 obj << /Border [0 0 0] /Dest (_mul) /Subtype /Link @@ -87337,7 +87472,7 @@ endobj /Type /Annot >> endobj -816 0 obj +817 0 obj << /Border [0 0 0] /Dest (_mul) /Subtype /Link @@ -87345,7 +87480,7 @@ endobj /Type /Annot >> endobj -817 0 obj +818 0 obj << /Border [0 0 0] /Dest (_mulh) /Subtype /Link @@ -87353,7 +87488,7 @@ endobj /Type /Annot >> endobj -818 0 obj +819 0 obj << /Border [0 0 0] /Dest (_mulh) /Subtype /Link @@ -87361,7 +87496,7 @@ endobj /Type /Annot >> endobj -819 0 obj +820 0 obj << /Border [0 0 0] /Dest (_mulhsu) /Subtype /Link @@ -87369,7 +87504,7 @@ endobj /Type /Annot >> endobj -820 0 obj +821 0 obj << /Border [0 0 0] /Dest (_mulhsu) /Subtype /Link @@ -87377,7 +87512,7 @@ endobj /Type /Annot >> endobj -821 0 obj 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+0001399933 00000 n +0001401289 00000 n +0001402206 00000 n +0001406123 00000 n +0001406339 00000 n +0001406663 00000 n +0001407580 00000 n +0001414221 00000 n +0001414447 00000 n +0001415803 00000 n trailer -<< /Size 1138 +<< /Size 1139 /Root 2 0 R /Info 1 0 R >> startxref -1414744 +1416719 %%EOF diff --git a/doc/sections/configuration_and_integration.adoc b/doc/sections/configuration_and_integration.adoc index 7e3dbed..1cc2927 100644 --- a/doc/sections/configuration_and_integration.adoc +++ b/doc/sections/configuration_and_integration.adoc @@ -73,28 +73,28 @@ Default value: 1 Support for Zba address generation instructions. 0 for disable, 1 for enable. -Default value: 1 +Default value: 0 [[param-EXTENSION_ZBB]] ===== EXTENSION_ZBB Support for Zbb basic bit manipulation instructions. 0 for disable, 1 for enable. -Default value: 1 +Default value: 0 [[param-EXTENSION_ZBC]] ===== EXTENSION_ZBC Support for Zbc carry-less multiplication instructions. 0 for disable, 1 for enable. -Default value: 1 +Default value: 0 [[param-EXTENSION_ZBS]] ===== EXTENSION_ZBS Support for Zbs single-bit manipulation instructions. 0 for disable, 1 for enable. -Default value: 1 +Default value: 0 [[param-EXTENSION_ZBKB]] ===== EXTENSION_ZBKB @@ -103,7 +103,7 @@ Support for Zbkb basic bit manipulation for cryptography. Requires: <>. (Since Zbb and Zbkb have a large overlap, this flag enables only those instructions which are in Zbkb but aren't in Zbb. Therefore both flags must be set for full Zbkb support.) -Default value: 1 +Default value: 0 [[param-EXTENSION_ZIFENCEI]] ===== EXTENSION_ZIFENCEI @@ -113,17 +113,17 @@ this instruction is optional, since a plain branch/jump is sufficient to flush the instruction prefetch queue. When the branch predictor is enabled (<> is 1), this instruction must be implemented. -Default value: 1 +Default value: 0 + +[[cfg-custom-extensions]] +==== Custom Hazard3 Extensions [[param-EXTENSION_XH3BEXTM]] ===== EXTENSION_XH3BEXTM Custom bit manipulation instructions for Hazard3: `h3.bextm` and `h3.bextmi`. See <>. -Default value: 1 - -[[cfg-custom-extensions]] -==== Custom Hazard3 Extensions +Default value: 0 [[param-EXTENSION_XH3IRQ]] ===== EXTENSION_XH3IRQ @@ -132,21 +132,21 @@ Custom preemptive, prioritised interrupt support. Can be disabled if an external interrupt controller (e.g. PLIC) is used. If disabled, and NUM_IRQS > 1, the external interrupts are simply OR'd into mip.meip. See <>. -Default value: 1 - +Default value: 0 [[param-EXTENSION_XH3PMPM]] ===== EXTENSION_XH3PMPM Custom PMPCFGMx CSRs to enforce PMP regions in M-mode without locking. See <>. +Default value: 0 [[param-EXTENSION_XH3POWER]] ===== EXTENSION_XH3POWER Custom power management controls for Hazard3. This adds the <> CSR, and the `h3.block` and `h3.unblock` hint instructions. See <> -Default value: 1 +Default value: 0 ==== CSR support @@ -162,16 +162,22 @@ the privileged specification itself is an optional extension. Hazard3 allows the mandatory CSRs to be disabled to save a small amount of area in deeply-embedded implementations. +Default value: 1 + [[param-CSR_M_TRAP]] ===== CSR_M_TRAP Include M-mode trap-handling CSRs, and enable trap support. +Default value: 1 + [[param-CSR_COUNTER]] ===== CSR_COUNTER Include the basic performance counters (`cycle`/`instret`) and relevant CSRs. Note that these performance counters are now in their own separate extension (Zicntr) and are no longer mandatory. +Default value: 0 + [[param-U_MODE]] ===== U_MODE @@ -182,22 +188,26 @@ memory. Requires: <>. +Default value: 0 + [[param-PMP_REGIONS]] ===== PMP_REGIONS Number of physical memory protection regions, or 0 for no PMP. PMP is more -useful if U mode is supported, but this is not a requirement. +useful if U-mode is supported, but this is not a requirement. Hazard3's PMP supports only the NAPOT and(if <> is 0) NA4 region types. Requires: <>. +Default value: 0 + [[param-PMP_GRAIN]] ===== PMP_GRAIN This is the _G_ parameter in the privileged spec, which defines the -granularity of PMP regions. Minimum PMP region size is 1 <<(_G_ + 2) bytes. +granularity of PMP regions. Minimum PMP region size is 1 << (_G_ + 2) bytes. If _G_ > 0, `pmcfg.a` can not be set to NA4 (attempting to do so will set the region to OFF instead). @@ -266,18 +276,19 @@ Default value: 0 [[param-NUM_IRQS]] ===== NUM_IRQS -Number of external IRQs implemented in meiea, meipa, meifa and meipra, if -<> is enabled. Minimum 1, maximum 512. +NUM_IRQS: Number of external IRQs. Minimum 1, maximum 512. Note that if +<> (Hazard3 interrupt controller) is disabled then +multiple external interrupts are simply OR'd into mip.meip. -Default value: 32 +Default value: 1 [[param-IRQ_PRIORITY_BITS]] ===== IRQ_PRIORITY_BITS -Number of priority bits implemented for each interrupt in meipra. The -number of distinct levels is (1 << IRQ_PRIORITY_BITS). Minimum 0, max 4. -Note that having more than 1 priority level with a large number of IRQs -will have a severe effect on timing. +IRQ_PRIORITY_BITS: Number of priority bits implemented for each interrupt +in meipra, if EXTENSION_XH3IRQ is enabled. The number of distinct levels +is (1 << IRQ_PRIORITY_BITS). Minimum 0, max 4. Note that multiple priority +levels with a large number of IRQs will have a severe effect on timing. Default value: 0 @@ -285,7 +296,9 @@ Default value: 0 ===== IRQ_INPUT_BYPASS Disable the input registers on the external interrupts, to reduce latency by -one cycle. Can be done on an IRQ-by-IRQ basis. +one cycle. Can be applied on an IRQ-by-IRQ basis. + +Ignored if <> is disabled. Default value: all-zeroes (not bypassed). @@ -397,7 +410,7 @@ nontaken branch, a fence.i or a trap. Successful prediction eliminates the Requires: <> -Default value: 1 +Default value: 0 [[param-MTVEC_WMASK]] ===== MTVEC_WMASK diff --git a/hdl/hazard3_config.vh b/hdl/hazard3_config.vh index 17da5b4..97f0142 100644 --- a/hdl/hazard3_config.vh +++ b/hdl/hazard3_config.vh @@ -43,43 +43,43 @@ parameter EXTENSION_C = 1, parameter EXTENSION_M = 1, // EXTENSION_ZBA: Support for Zba address generation instructions -parameter EXTENSION_ZBA = 1, +parameter EXTENSION_ZBA = 0, // EXTENSION_ZBB: Support for Zbb basic bit manipulation instructions -parameter EXTENSION_ZBB = 1, +parameter EXTENSION_ZBB = 0, // EXTENSION_ZBC: Support for Zbc carry-less multiplication instructions -parameter EXTENSION_ZBC = 1, +parameter EXTENSION_ZBC = 0, // EXTENSION_ZBS: Support for Zbs single-bit manipulation instructions -parameter EXTENSION_ZBS = 1, +parameter EXTENSION_ZBS = 0, // EXTENSION_ZBKB: Support for Zbkb basic bit manipulation for cryptography // Requires: Zbb. (This flag enables instructions in Zbkb which aren't in Zbb.) -parameter EXTENSION_ZBKB = 1, +parameter EXTENSION_ZBKB = 0, // EXTENSION_ZIFENCEI: Support for the fence.i instruction // Optional, since a plain branch/jump will also flush the prefetch queue. -parameter EXTENSION_ZIFENCEI = 1, +parameter EXTENSION_ZIFENCEI = 0, // ---------------------------------------------------------------------------- // Custom RISC-V extensions // EXTENSION_XH3B: Custom bit-extract-multiple instructions for Hazard3 -parameter EXTENSION_XH3BEXTM = 1, +parameter EXTENSION_XH3BEXTM = 0, // EXTENSION_XH3IRQ: Custom preemptive, prioritised interrupt support. Can be // disabled if an external interrupt controller (e.g. PLIC) is used. If // disabled, and NUM_IRQS > 1, the external interrupts are simply OR'd into // mip.meip. -parameter EXTENSION_XH3IRQ = 1, +parameter EXTENSION_XH3IRQ = 0, // EXTENSION_XH3PMPM: PMPCFGMx CSRs to enforce PMP regions in M-mode without // locking. Unlike ePMP mseccfg.rlb, locked and unlocked regions can coexist -parameter EXTENSION_XH3PMPM = 1, +parameter EXTENSION_XH3PMPM = 0, // EXTENSION_XH3POWER: Custom power management controls for Hazard3 -parameter EXTENSION_XH3POWER = 1, +parameter EXTENSION_XH3POWER = 0, // ---------------------------------------------------------------------------- // Standard CSR support @@ -94,8 +94,8 @@ parameter CSR_M_MANDATORY = 1, // CSR_M_TRAP: Include M-mode trap-handling CSRs, and enable trap support. parameter CSR_M_TRAP = 1, -// CSR_COUNTER: Include performance counters and relevant M-mode CSRs -parameter CSR_COUNTER = 1, +// CSR_COUNTER: Include performance counters and Zicntr CSRs +parameter CSR_COUNTER = 0, // U_MODE: Support the U (user) execution mode. In U mode, the core performs // unprivileged bus accesses, and software's access to CSRs is restricted. @@ -140,19 +140,20 @@ parameter BREAKPOINT_TRIGGERS = 0, // ---------------------------------------------------------------------------- // External interrupt support -// NUM_IRQS: Number of external IRQs implemented in meiea, meipa, meifa and -// meipra, if CSR_M_TRAP is enabled. Minimum 1, maximum 512. -parameter NUM_IRQS = 32, +// NUM_IRQS: Number of external IRQs. Minimum 1, maximum 512. Note that if +// EXTENSION_XH3IRQ (Hazard3 interrupt controller) is disabled then multiple +// external interrupts are simply OR'd into mip.meip. +parameter NUM_IRQS = 1, // IRQ_PRIORITY_BITS: Number of priority bits implemented for each interrupt -// in meipra. The number of distinct levels is (1 << IRQ_PRIORITY_BITS). -// Minimum 0, max 4. Note that having more than 1 priority level with a large -// number of IRQs will have a severe effect on timing. Ignored if -// EXTENSION_XH3IRQ is disabled. +// in meipra, if EXTENSION_XH3IRQ is enabled. The number of distinct levels +// is (1 << IRQ_PRIORITY_BITS). Minimum 0, max 4. Note that multiple priority +// levels with a large number of IRQs will have a severe effect on timing. parameter IRQ_PRIORITY_BITS = 0, // IRQ_INPUT_BYPASS: disable the input registers on the external interrupts, -// to reduce latency by one cycle. Can be done on an IRQ-by-IRQ basis. +// to reduce latency by one cycle. Can be applied on an IRQ-by-IRQ basis. +// Ignored if EXTENSION_XH3IRQ is disabled. parameter IRQ_INPUT_BYPASS = {NUM_IRQS{1'b0}}, // ---------------------------------------------------------------------------- @@ -213,7 +214,7 @@ parameter RESET_REGFILE = 1, // cleared on a mispredicted nontaken branch, a fence.i or a trap. Successful // prediction eliminates the 1-cyle fetch bubble on a taken branch, usually // making tight loops faster. -parameter BRANCH_PREDICTOR = 1, +parameter BRANCH_PREDICTOR = 0, // MTVEC_WMASK: Mask of which bits in mtvec are writable. Full writability is // recommended, because a common idiom in setup code is to set mtvec just