diff --git a/hdl/hazard3_core.v b/hdl/hazard3_core.v
index 11ab9fd..4c62c40 100644
--- a/hdl/hazard3_core.v
+++ b/hdl/hazard3_core.v
@@ -140,6 +140,7 @@ end
 //synthesis translate_on
 
 // To X
+wire                 d_starved;
 wire [W_DATA-1:0]    d_imm;
 wire [W_REGADDR-1:0] d_rs1;
 wire [W_REGADDR-1:0] d_rs2;
@@ -174,6 +175,7 @@ hazard3_decode #(
 	.d_pc                 (d_pc),
 	.x_jump_not_except    (x_jump_not_except),
 
+	.d_starved            (d_starved),
 	.d_stall              (d_stall),
 	.x_stall              (x_stall),
 	.f_jump_rdy           (f_jump_rdy),
@@ -674,9 +676,9 @@ hazard3_regfile_1w2r #(
 	.rst_n  (rst_n),
 	// On downstream stall, we feed D's addresses back into regfile
 	// so that output does not change.
-	.raddr1 (x_stall ? d_rs1 : f_rs1),
+	.raddr1 (x_stall && !d_starved ? d_rs1 : f_rs1),
 	.rdata1 (x_rdata1),
-	.raddr2 (x_stall ? d_rs2 : f_rs2),
+	.raddr2 (x_stall && !d_starved ? d_rs2 : f_rs2),
 	.rdata2 (x_rdata2),
 
 	.waddr  (xm_rd),
diff --git a/hdl/hazard3_decode.v b/hdl/hazard3_decode.v
index f23955c..7ba00ab 100644
--- a/hdl/hazard3_decode.v
+++ b/hdl/hazard3_decode.v
@@ -31,6 +31,7 @@ module hazard3_decode #(
 	output wire                 df_cir_lock,
 	output wire [W_ADDR-1:0]    d_pc,
 
+	output wire                 d_starved,
 	output wire                 d_stall,
 	input wire                  x_stall,
 	input wire                  f_jump_rdy,
@@ -91,7 +92,7 @@ wire [31:0] d_imm_j = {{12{d_instr[31]}}, d_instr[19:12], d_instr[20], d_instr[3
 // ----------------------------------------------------------------------------
 // PC/CIR control
 
-wire d_starved = ~|fd_cir_vld || fd_cir_vld[0] && d_instr_is_32bit;
+assign d_starved = ~|fd_cir_vld || fd_cir_vld[0] && d_instr_is_32bit;
 assign d_stall = x_stall || d_starved;
 
 assign df_cir_use =