From 4c098d76a7bb3c7c99efe69c81d4a3c90348d8fc Mon Sep 17 00:00:00 2001 From: Luke Wren Date: Sun, 21 Aug 2022 13:09:28 +0100 Subject: [PATCH] Fix some whitespace issues, and avoid redefinition of RVOPC macros --- hdl/hazard3_csr.v | 56 ++++++++++++------------- hdl/rv_opcodes.vh | 101 ++++++++++++++++++++++++---------------------- 2 files changed, 81 insertions(+), 76 deletions(-) diff --git a/hdl/hazard3_csr.v b/hdl/hazard3_csr.v index 4ef9675..5e699b9 100644 --- a/hdl/hazard3_csr.v +++ b/hdl/hazard3_csr.v @@ -639,7 +639,7 @@ always @ (*) begin pmp_cfg_wen = 1'b0; case (addr) - // ------------------------------------------------------------------------ + // ------------------------------------------------------------------------ // Mandatory CSRs MISA: if (CSR_M_MANDATORY) begin @@ -731,7 +731,7 @@ always @ (*) begin decode_match = match_mrw; end - // ------------------------------------------------------------------------ + // ------------------------------------------------------------------------ // Trap-handling CSRs // This is a 32 bit synthesised register with set/clear/write/read, don't @@ -780,7 +780,7 @@ always @ (*) begin }; end - // ------------------------------------------------------------------------ + // ------------------------------------------------------------------------ // Counter CSRs // Get the tied WARLs out the way first @@ -912,11 +912,11 @@ always @ (*) begin }; end - // ------------------------------------------------------------------------ - // PMP CSRs (bridge to PMP config interface) + // ------------------------------------------------------------------------ + // PMP CSRs (bridge to PMP config interface) - // If PMP is present, all 16 registers are present, but some may be WARL'd - // to 0 depending on how many regions are actually implemented. + // If PMP is present, all 16 registers are present, but some may be WARL'd + // to 0 depending on how many regions are actually implemented. PMPCFG0: if (PMP_REGIONS > 0) begin decode_match = match_mrw; pmp_cfg_wen = match_mrw && wen; @@ -1021,28 +1021,28 @@ always @ (*) begin // MSECCFG is strictly optional, and we don't implement any of its // features (ePMP etc) so we don't decode it. - // ------------------------------------------------------------------------ - // U-mode CSRs + // ------------------------------------------------------------------------ + // U-mode CSRs - // The read-only counters are always visible to M mode, and are visible to - // U mode if the corresponding mcounteren bit is set. - CYCLE: if (CSR_COUNTER) begin - decode_match = mcounteren_cy ? match_uro : match_mro; - rdata = mcycle; - end - CYCLEH: if (CSR_COUNTER) begin - decode_match = mcounteren_cy ? match_uro : match_mro; - rdata = mcycleh; - end + // The read-only counters are always visible to M mode, and are visible to + // U mode if the corresponding mcounteren bit is set. + CYCLE: if (CSR_COUNTER) begin + decode_match = mcounteren_cy ? match_uro : match_mro; + rdata = mcycle; + end + CYCLEH: if (CSR_COUNTER) begin + decode_match = mcounteren_cy ? match_uro : match_mro; + rdata = mcycleh; + end - INSTRET: if (CSR_COUNTER) begin - decode_match = mcounteren_ir ? match_uro : match_mro; - rdata = minstret; - end - INSTRETH: if (CSR_COUNTER) begin - decode_match = mcounteren_ir ? match_uro : match_mro; - rdata = minstreth; - end + INSTRET: if (CSR_COUNTER) begin + decode_match = mcounteren_ir ? match_uro : match_mro; + rdata = minstret; + end + INSTRETH: if (CSR_COUNTER) begin + decode_match = mcounteren_ir ? match_uro : match_mro; + rdata = minstreth; + end // ------------------------------------------------------------------------ // Trigger Module CSRs @@ -1088,7 +1088,7 @@ always @ (*) begin rdata = dbg_data0_rdata; end - // ------------------------------------------------------------------------ + // ------------------------------------------------------------------------ // Custom CSRs MEIEA: if (CSR_M_TRAP) begin diff --git a/hdl/rv_opcodes.vh b/hdl/rv_opcodes.vh index 41d08a0..73aa4cc 100644 --- a/hdl/rv_opcodes.vh +++ b/hdl/rv_opcodes.vh @@ -15,6 +15,9 @@ localparam RV_RD_BITS = 5; // for whether Z values are propagated through a localparam to a casez. // Multiple tools complain about it, so just this once I'll use macros. +`ifndef HAZARD3_RVOPC_MACROS +`define HAZARD3_RVOPC_MACROS + // Base ISA (some of these are Z now) `define RVOPC_BEQ 32'b?????????????????000?????1100011 `define RVOPC_BNE 32'b?????????????????001?????1100011 @@ -180,51 +183,53 @@ localparam RV_RD_BITS = 5; // Copies provided here with 0 instead of ? so that these can be used to build 32-bit instructions in the decompressor -`define RVOPC_NOZ_BEQ 32'b00000000000000000000000001100011 -`define RVOPC_NOZ_BNE 32'b00000000000000000001000001100011 -`define RVOPC_NOZ_BLT 32'b00000000000000000100000001100011 -`define RVOPC_NOZ_BGE 32'b00000000000000000101000001100011 -`define RVOPC_NOZ_BLTU 32'b00000000000000000110000001100011 -`define RVOPC_NOZ_BGEU 32'b00000000000000000111000001100011 -`define RVOPC_NOZ_JALR 32'b00000000000000000000000001100111 -`define RVOPC_NOZ_JAL 32'b00000000000000000000000001101111 -`define RVOPC_NOZ_LUI 32'b00000000000000000000000000110111 -`define RVOPC_NOZ_AUIPC 32'b00000000000000000000000000010111 -`define RVOPC_NOZ_ADDI 32'b00000000000000000000000000010011 -`define RVOPC_NOZ_SLLI 32'b00000000000000000001000000010011 -`define RVOPC_NOZ_SLTI 32'b00000000000000000010000000010011 -`define RVOPC_NOZ_SLTIU 32'b00000000000000000011000000010011 -`define RVOPC_NOZ_XORI 32'b00000000000000000100000000010011 -`define RVOPC_NOZ_SRLI 32'b00000000000000000101000000010011 -`define RVOPC_NOZ_SRAI 32'b01000000000000000101000000010011 -`define RVOPC_NOZ_ORI 32'b00000000000000000110000000010011 -`define RVOPC_NOZ_ANDI 32'b00000000000000000111000000010011 -`define RVOPC_NOZ_ADD 32'b00000000000000000000000000110011 -`define RVOPC_NOZ_SUB 32'b01000000000000000000000000110011 -`define RVOPC_NOZ_SLL 32'b00000000000000000001000000110011 -`define RVOPC_NOZ_SLT 32'b00000000000000000010000000110011 -`define RVOPC_NOZ_SLTU 32'b00000000000000000011000000110011 -`define RVOPC_NOZ_XOR 32'b00000000000000000100000000110011 -`define RVOPC_NOZ_SRL 32'b00000000000000000101000000110011 -`define RVOPC_NOZ_SRA 32'b01000000000000000101000000110011 -`define RVOPC_NOZ_OR 32'b00000000000000000110000000110011 -`define RVOPC_NOZ_AND 32'b00000000000000000111000000110011 -`define RVOPC_NOZ_LB 32'b00000000000000000000000000000011 -`define RVOPC_NOZ_LH 32'b00000000000000000001000000000011 -`define RVOPC_NOZ_LW 32'b00000000000000000010000000000011 -`define RVOPC_NOZ_LBU 32'b00000000000000000100000000000011 -`define RVOPC_NOZ_LHU 32'b00000000000000000101000000000011 -`define RVOPC_NOZ_SB 32'b00000000000000000000000000100011 -`define RVOPC_NOZ_SH 32'b00000000000000000001000000100011 -`define RVOPC_NOZ_SW 32'b00000000000000000010000000100011 -`define RVOPC_NOZ_FENCE 32'b00000000000000000000000000001111 -`define RVOPC_NOZ_FENCE_I 32'b00000000000000000001000000001111 -`define RVOPC_NOZ_ECALL 32'b00000000000000000000000001110011 -`define RVOPC_NOZ_EBREAK 32'b00000000000100000000000001110011 -`define RVOPC_NOZ_CSRRW 32'b00000000000000000001000001110011 -`define RVOPC_NOZ_CSRRS 32'b00000000000000000010000001110011 -`define RVOPC_NOZ_CSRRC 32'b00000000000000000011000001110011 -`define RVOPC_NOZ_CSRRWI 32'b00000000000000000101000001110011 -`define RVOPC_NOZ_CSRRSI 32'b00000000000000000110000001110011 -`define RVOPC_NOZ_CSRRCI 32'b00000000000000000111000001110011 -`define RVOPC_NOZ_SYSTEM 32'b00000000000000000000000001110011 +`define RVOPC_NOZ_BEQ 32'b00000000000000000000000001100011 +`define RVOPC_NOZ_BNE 32'b00000000000000000001000001100011 +`define RVOPC_NOZ_BLT 32'b00000000000000000100000001100011 +`define RVOPC_NOZ_BGE 32'b00000000000000000101000001100011 +`define RVOPC_NOZ_BLTU 32'b00000000000000000110000001100011 +`define RVOPC_NOZ_BGEU 32'b00000000000000000111000001100011 +`define RVOPC_NOZ_JALR 32'b00000000000000000000000001100111 +`define RVOPC_NOZ_JAL 32'b00000000000000000000000001101111 +`define RVOPC_NOZ_LUI 32'b00000000000000000000000000110111 +`define RVOPC_NOZ_AUIPC 32'b00000000000000000000000000010111 +`define RVOPC_NOZ_ADDI 32'b00000000000000000000000000010011 +`define RVOPC_NOZ_SLLI 32'b00000000000000000001000000010011 +`define RVOPC_NOZ_SLTI 32'b00000000000000000010000000010011 +`define RVOPC_NOZ_SLTIU 32'b00000000000000000011000000010011 +`define RVOPC_NOZ_XORI 32'b00000000000000000100000000010011 +`define RVOPC_NOZ_SRLI 32'b00000000000000000101000000010011 +`define RVOPC_NOZ_SRAI 32'b01000000000000000101000000010011 +`define RVOPC_NOZ_ORI 32'b00000000000000000110000000010011 +`define RVOPC_NOZ_ANDI 32'b00000000000000000111000000010011 +`define RVOPC_NOZ_ADD 32'b00000000000000000000000000110011 +`define RVOPC_NOZ_SUB 32'b01000000000000000000000000110011 +`define RVOPC_NOZ_SLL 32'b00000000000000000001000000110011 +`define RVOPC_NOZ_SLT 32'b00000000000000000010000000110011 +`define RVOPC_NOZ_SLTU 32'b00000000000000000011000000110011 +`define RVOPC_NOZ_XOR 32'b00000000000000000100000000110011 +`define RVOPC_NOZ_SRL 32'b00000000000000000101000000110011 +`define RVOPC_NOZ_SRA 32'b01000000000000000101000000110011 +`define RVOPC_NOZ_OR 32'b00000000000000000110000000110011 +`define RVOPC_NOZ_AND 32'b00000000000000000111000000110011 +`define RVOPC_NOZ_LB 32'b00000000000000000000000000000011 +`define RVOPC_NOZ_LH 32'b00000000000000000001000000000011 +`define RVOPC_NOZ_LW 32'b00000000000000000010000000000011 +`define RVOPC_NOZ_LBU 32'b00000000000000000100000000000011 +`define RVOPC_NOZ_LHU 32'b00000000000000000101000000000011 +`define RVOPC_NOZ_SB 32'b00000000000000000000000000100011 +`define RVOPC_NOZ_SH 32'b00000000000000000001000000100011 +`define RVOPC_NOZ_SW 32'b00000000000000000010000000100011 +`define RVOPC_NOZ_FENCE 32'b00000000000000000000000000001111 +`define RVOPC_NOZ_FENCE_I 32'b00000000000000000001000000001111 +`define RVOPC_NOZ_ECALL 32'b00000000000000000000000001110011 +`define RVOPC_NOZ_EBREAK 32'b00000000000100000000000001110011 +`define RVOPC_NOZ_CSRRW 32'b00000000000000000001000001110011 +`define RVOPC_NOZ_CSRRS 32'b00000000000000000010000001110011 +`define RVOPC_NOZ_CSRRC 32'b00000000000000000011000001110011 +`define RVOPC_NOZ_CSRRWI 32'b00000000000000000101000001110011 +`define RVOPC_NOZ_CSRRSI 32'b00000000000000000110000001110011 +`define RVOPC_NOZ_CSRRCI 32'b00000000000000000111000001110011 +`define RVOPC_NOZ_SYSTEM 32'b00000000000000000000000001110011 + +`endif