From 4c12f163bdfa903a2682955acd21a8d760693bf9 Mon Sep 17 00:00:00 2001 From: Scott Shawcroft Date: Sat, 17 Dec 2022 03:49:41 -0800 Subject: [PATCH] Add OrangeCrab 25F support (#7) * Add OrangeCrab 25F support * Fix whitespace Co-authored-by: Luke Wren --- example_soc/fpga/fpga_orangecrab_25f.f | 10 +++ example_soc/fpga/fpga_orangecrab_25f.v | 98 +++++++++++++++++++++++ example_soc/synth/fpga_orangecrab_25f.lpf | 44 ++++++++++ example_soc/synth/orangecrab-25f.mk | 23 ++++++ 4 files changed, 175 insertions(+) create mode 100644 example_soc/fpga/fpga_orangecrab_25f.f create mode 100644 example_soc/fpga/fpga_orangecrab_25f.v create mode 100644 example_soc/synth/fpga_orangecrab_25f.lpf create mode 100644 example_soc/synth/orangecrab-25f.mk diff --git a/example_soc/fpga/fpga_orangecrab_25f.f b/example_soc/fpga/fpga_orangecrab_25f.f new file mode 100644 index 0000000..664fa45 --- /dev/null +++ b/example_soc/fpga/fpga_orangecrab_25f.f @@ -0,0 +1,10 @@ +file fpga_orangecrab_25f.v +file ../libfpga/common/reset_sync.v +file ../libfpga/common/fpga_reset.v + +list ../soc/soc.f + +# ECP5 DTM is not in main SoC list because the JTAGG primitive doesn't exist +# on most platforms +list ../../hdl/debug/dtm/hazard3_ecp5_jtag_dtm.f + diff --git a/example_soc/fpga/fpga_orangecrab_25f.v b/example_soc/fpga/fpga_orangecrab_25f.v new file mode 100644 index 0000000..f4cdd6f --- /dev/null +++ b/example_soc/fpga/fpga_orangecrab_25f.v @@ -0,0 +1,98 @@ +/*****************************************************************************\ +| Copyright (C) 2021 Luke Wren | +| SPDX-License-Identifier: Apache-2.0 | +\*****************************************************************************/ + +`default_nettype none + +module fpga_orangecrab_25f ( + input wire clk_osc, + output wire [7:0] dbg, + + output wire uart_tx, + input wire uart_rx, + + output rgb_led0_r, + output rgb_led0_g, + output rgb_led0_b, + + output rst_n, + input usr_btn +); + +wire clk_sys = clk_osc; +wire rst_n_sys; +wire trst_n; + +fpga_reset #( + .SHIFT (3) +) rstgen ( + .clk (clk_sys), + .force_rst_n (1'b1), + .rst_n (rst_n_sys) +); + +example_soc #( + .DTM_TYPE ("ECP5"), + .SRAM_DEPTH (1 << 14), + .CLK_MHZ (48), + + .EXTENSION_M (1), + .EXTENSION_A (1), + .EXTENSION_C (0), + .EXTENSION_ZBA (0), + .EXTENSION_ZBB (0), + .EXTENSION_ZBC (0), + .EXTENSION_ZBS (0), + .EXTENSION_ZBKB (0), + .EXTENSION_ZIFENCEI (1), + .EXTENSION_XH3BEXTM (0), + .EXTENSION_XH3PMPM (0), + .EXTENSION_XH3POWER (0), + .CSR_COUNTER (1), + .MUL_FAST (1), + .MUL_FASTER (0), + .MULH_FAST (0), + .MULDIV_UNROLL (1), + .FAST_BRANCHCMP (1), + .BRANCH_PREDICTOR (1) +) soc_u ( + .clk (clk_sys), + .rst_n (rst_n_sys), + + // JTAG connections provided internally by ECP5 JTAGG primitive + .tck (1'b0), + .trst_n (1'b0), + .tms (1'b0), + .tdi (1'b0), + .tdo (/* unused */), + + .uart_tx (uart_tx), + .uart_rx (uart_rx) +); + + // Create a 27 bit register + reg [26:0] counter = 0; + + // Every positive edge increment register by 1 + always @(posedge clk_sys) begin + counter <= counter + 1; + end + + // Output inverted values of counter onto LEDs + assign rgb_led0_r = ~counter[24]; + assign rgb_led0_g = ~counter[25]; + assign rgb_led0_b = 0; + + assign dbg = 8'hff; + + // Reset logic on button press. + // this will enter the bootloader + reg reset_sr = 1'b1; + always @(posedge clk_sys) begin + reset_sr <= {usr_btn}; + end + assign rst_n = reset_sr; + + +endmodule diff --git a/example_soc/synth/fpga_orangecrab_25f.lpf b/example_soc/synth/fpga_orangecrab_25f.lpf new file mode 100644 index 0000000..7dd583f --- /dev/null +++ b/example_soc/synth/fpga_orangecrab_25f.lpf @@ -0,0 +1,44 @@ +# Reference: https://github.com/emard/ulx3s/blob/master/doc/constraints/ulx3s_v20.lpf + +LOCATE COMP "clk_osc" SITE "A9"; +IOBUF PORT "clk_osc" PULLMODE=NONE IO_TYPE=LVCMOS33; +FREQUENCY PORT "clk_osc" 48 MHZ; + +# UART TX/RX (from FPGA's point of view, i.e. TX is an output) + +LOCATE COMP "uart_tx" SITE "N17"; # FPGA transmits to ftdi +LOCATE COMP "uart_rx" SITE "M18"; # FPGA receives from ftdi +IOBUF PORT "uart_tx" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "uart_rx" PULLMODE=UP IO_TYPE=LVCMOS33; + +# 8 pins on an IO header for bringing signals out to a logic analyser + +LOCATE COMP "dbg[0]" SITE "H2"; # PCLK # "gn[0]" +LOCATE COMP "dbg[1]" SITE "A8"; # PCLK # "gn[1]" +LOCATE COMP "dbg[2]" SITE "B8"; # GR_PCLK # "gn[2]" +LOCATE COMP "dbg[3]" SITE "C8"; # "gn[3]" +LOCATE COMP "dbg[4]" SITE "B9"; # PCLK # "gp[0]" +LOCATE COMP "dbg[5]" SITE "B10"; # PCLK # "gp[1]" +LOCATE COMP "dbg[6]" SITE "L4"; # GR_PCLK # "gp[2]" +LOCATE COMP "dbg[7]" SITE "N3"; # "gp[3]" + +IOBUF PORT "dbg[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "dbg[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "dbg[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "dbg[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "dbg[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "dbg[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "dbg[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "dbg[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +LOCATE COMP "rgb_led0_r" SITE "K4"; +IOBUF PORT "rgb_led0_r" IO_TYPE=LVCMOS33; +LOCATE COMP "rgb_led0_g" SITE "M3"; +IOBUF PORT "rgb_led0_g" IO_TYPE=LVCMOS33; +LOCATE COMP "rgb_led0_b" SITE "J3"; +IOBUF PORT "rgb_led0_b" IO_TYPE=LVCMOS33; + +LOCATE COMP "usr_btn" SITE "J17"; +IOBUF PORT "usr_btn" IO_TYPE=SSTL135_I; +LOCATE COMP "rst_n" SITE "V17"; +IOBUF PORT "rst_n" IO_TYPE=LVCMOS33; diff --git a/example_soc/synth/orangecrab-25f.mk b/example_soc/synth/orangecrab-25f.mk new file mode 100644 index 0000000..957ce94 --- /dev/null +++ b/example_soc/synth/orangecrab-25f.mk @@ -0,0 +1,23 @@ +CHIPNAME=fpga_orangecrab_25f +TOP=fpga_orangecrab_25f +DOTF=../fpga/fpga_orangecrab_25f.f + +SYNTH_OPT=-abc9 +PNR_OPT=--timing-allow-fail + +DEVICE=25k +PACKAGE=CSFBGA285 + +DEVICE_IDCODE=0x41111043 + +include $(SCRIPTS)/synth_ecp5.mk + +$(CHIPNAME).dfu: bit + cp $(CHIPNAME).bit $@ + dfu-suffix -v 1209 -p 5af0 -a $@ + +prog: bit + ujprog $(CHIPNAME).bit + +flash: $(CHIPNAME).dfu + dfu-util -d 1209:5af0 -D $<