diff --git a/hdl/hazard3_core.v b/hdl/hazard3_core.v
index 98e5095..c1429af 100644
--- a/hdl/hazard3_core.v
+++ b/hdl/hazard3_core.v
@@ -604,7 +604,8 @@ always @ (posedge clk or negedge rst_n) begin
 		// taken once this load/store moves to the next stage: if another load/store
 		// is chasing down the pipeline then this is immediately suppressed by the
 		// IRQ entry, before its address phase can begin.
-		xm_delay_irq_entry <= bus_aph_req_d && !bus_aph_ready_d;
+		xm_delay_irq_entry <= bus_aph_req_d && !bus_aph_ready_d ||
+			d_memop_is_amo && (x_amo_phase == 3'h2 || x_amo_phase == 3'h3 && !bus_dph_ready_d);
 		if (!x_stall)
 			prev_instr_was_32_bit <= df_cir_use == 2'd2;
 	end