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List Zcb/Zcmp in docs, and rebuild PDF

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Luke Wren 2023-03-22 02:55:07 +00:00
parent b58cde882a
commit 56586def8d
4 changed files with 38241 additions and 39187 deletions
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77410
doc/hazard3.pdf
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10
doc/sections/configuration_and_integration.adoc
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@ -116,6 +116,16 @@ Note Zca is equivalent to C, as we do not support the F extension.
Default value: 0
[[param-EXTENSION_ZCMP]]
===== EXTENSION_ZCMP
Support for Zcmp push/pop and double-move instructions.
Requires: <<param-EXTENSION_C>>.
Note Zca is equivalent to C, as we do not support the F extension.
Default value: 0
[[param-EXTENSION_ZIFENCEI]]
===== EXTENSION_ZIFENCEI

4
doc/sections/introduction.adoc
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@ -12,6 +12,8 @@ Hazard3 is a configurable 3-stage RISC-V processor, implementing:
* `Zbc`: carry-less multiplication
* `Zbs`: single-bit manipulation
* `Zbkb`: basic bit manipulation for scalar cryptography
* `Zcb`: basic additional compressed instructions
* `Zcmp`: push/pop and double-move compressed instructions
* Debug, Machine and User privilege/execution modes
* Privileged instructions `ECALL`, `EBREAK`, `MRET` and `WFI`
* External debug support
@ -68,6 +70,8 @@ These are links to the ratified versions of the base instruction set and extensi
| `Zbc` v1.0.0 | https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0-38-g865e7a7.pdf[Bit Manipulation ISA extensions 20210628]
| `Zbs` v1.0.0 | https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0-38-g865e7a7.pdf[Bit Manipulation ISA extensions 20210628]
| `Zbkb` v1.0.1 | https://github.com/riscv/riscv-crypto/releases/download/v1.0.1-scalar/riscv-crypto-spec-scalar-v1.0.1.pdf[Scalar Cryptography ISA extensions 20220218]
| `Zcb` v1.0.3-1 | https://github.com/riscv/riscv-code-size-reduction/releases/download/v1.0.3-1/Zc-v1.0.3-1.pdf[Code Size Reduction extensions frozen v1.0.3-1]
| `Zcmp` v1.0.3-1 | https://github.com/riscv/riscv-code-size-reduction/releases/download/v1.0.3-1/Zc-v1.0.3-1.pdf[Code Size Reduction extensions frozen v1.0.3-1]
| Machine ISA v1.12 | https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf[Privileged Architecture 20211203]
| Debug v0.13.2 | https://riscv.org/wp-content/uploads/2019/03/riscv-debug-release.pdf[RISC-V External Debug Support 20190322]
|===

4
test/sim/sw_testcases/zcmp_irq_kill.c
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@ -52,9 +52,9 @@ void foreground_task() {
"lw s6, 40(sp)\n"
"lw s7, 44(sp)\n"
"lw s8, 48(sp)\n"
"lw s9, 52(sp)\n"
"lw s9, 52(sp)\n"
"lw s10, 56(sp)\n"
"lw s11, 60(sp)\n"
"lw s11, 60(sp)\n"
// Re-pop. Doing this a multiple of 13 times will restore the original contents.
".hword 0xbaf2\n" // cm.pop {ra, s0-s11},64
"addi a1, a1, -1\n"