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Implement data0 inside of DM instead of core, so it gets correct reset. Add dummy tselect CSR.

This commit is contained in:
Luke Wren 2021-07-16 18:28:30 +01:00
parent ce5152a4f4
commit 5aca6be572
5 changed files with 59 additions and 34 deletions
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37
hdl/debug/dm/hazard3_dm.v
View File

@ -66,9 +66,9 @@ module hazard3_dm #(
input wire [N_HARTS-1:0] hart_running,
// Hart access to data0 CSR (assumed to be core-internal but per-hart)
input wire [N_HARTS*XLEN-1:0] hart_data0_rdata,
output wire [N_HARTS*XLEN-1:0] hart_data0_wdata,
output wire [N_HARTS-1:0] hart_data0_wen,
output wire [N_HARTS*XLEN-1:0] hart_data0_rdata,
input wire [N_HARTS*XLEN-1:0] hart_data0_wdata,
input wire [N_HARTS-1:0] hart_data0_wen,
// Hart instruction injection
output wire [N_HARTS*XLEN-1:0] hart_instr_data,
@ -237,8 +237,33 @@ assign hart_req_resume = dmcontrol_resumereq_sticky;
wire abstractcs_busy;
assign hart_data0_wdata = {N_HARTS{dmi_pwdata}};
assign hart_data0_wen = {{N_HARTS-1{1'b0}}, dmi_write && dmi_paddr == ADDR_DATA0 && !abstractcs_busy} << hartsel;
// The same data0 register is aliased as a CSR on all harts connected to this
// DM. Cores may read data0 as a CSR when in debug mode, and may write it when:
//
// - That core is in debug mode, and...
// - We are currently executing an abstract command on that core
//
// The DM can also read/write data0 at all times.
reg [XLEN-1:0] abstract_data0;
assign hart_data0_rdata = {N_HARTS{abstract_data0}};
always @ (posedge clk or negedge rst_n) begin: update_hart_data0
integer i;
if (!rst_n) begin
abstract_data0 <= {XLEN{1'b0}};
end else if (!dmactive) begin
abstract_data0 <= {XLEN{1'b0}};
end else if (dmi_write && dmi_paddr == ADDR_DATA0) begin
abstract_data0 <= dmi_pwdata;
end else begin
for (i = 0; i < N_HARTS; i = i + 1) begin
if (hartsel == i && hart_data0_wen[i] && hart_halted[i] && abstractcs_busy)
abstract_data0 <= hart_data0_wdata[i * XLEN +: XLEN];
end
end
end
reg [XLEN-1:0] progbuf0;
reg [XLEN-1:0] progbuf1;
@ -464,7 +489,7 @@ assign hart_instr_data = {N_HARTS{
always @ (*) begin
case (dmi_paddr)
ADDR_DATA0: dmi_prdata = hart_data0_rdata[hartsel * XLEN +: XLEN];
ADDR_DATA0: dmi_prdata = abstract_data0;
ADDR_DMCONTROL: dmi_prdata = {
dmcontrol_haltreq[hartsel],
1'b0, // resumereq is a W1 field

6
hdl/hazard3_core.v
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@ -60,9 +60,9 @@ module hazard3_core #(
output wire dbg_halted,
output wire dbg_running,
// Debugger access to data0 CSR
output wire [W_DATA-1:0] dbg_data0_rdata,
input wire [W_DATA-1:0] dbg_data0_wdata,
input wire dbg_data0_wen,
input wire [W_DATA-1:0] dbg_data0_rdata,
output wire [W_DATA-1:0] dbg_data0_wdata,
output wire dbg_data0_wen,
// Debugger instruction injection
input wire [W_DATA-1:0] dbg_instr_data,
input wire dbg_instr_data_vld,

6
hdl/hazard3_cpu_1port.v
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@ -50,9 +50,9 @@ module hazard3_cpu_1port #(
output wire dbg_halted,
output wire dbg_running,
// Debugger access to data0 CSR
output wire [W_DATA-1:0] dbg_data0_rdata,
input wire [W_DATA-1:0] dbg_data0_wdata,
input wire dbg_data0_wen,
input wire [W_DATA-1:0] dbg_data0_rdata,
output wire [W_DATA-1:0] dbg_data0_wdata,
output wire dbg_data0_wen,
// Debugger instruction injection
input wire [W_DATA-1:0] dbg_instr_data,
input wire dbg_instr_data_vld,

6
hdl/hazard3_cpu_2port.v
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@ -63,9 +63,9 @@ module hazard3_cpu_2port #(
output wire dbg_halted,
output wire dbg_running,
// Debugger access to data0 CSR
output wire [W_DATA-1:0] dbg_data0_rdata,
input wire [W_DATA-1:0] dbg_data0_wdata,
input wire dbg_data0_wen,
input wire [W_DATA-1:0] dbg_data0_rdata,
output wire [W_DATA-1:0] dbg_data0_wdata,
output wire dbg_data0_wen,
// Debugger instruction injection
input wire [W_DATA-1:0] dbg_instr_data,
input wire dbg_instr_data_vld,

38
hdl/hazard3_csr.v
View File

@ -43,9 +43,9 @@ module hazard3_csr #(
output wire dbg_instr_caught_exception,
output wire dbg_instr_caught_ebreak,
output wire [W_DATA-1:0] dbg_data0_rdata,
input wire [W_DATA-1:0] dbg_data0_wdata,
input wire dbg_data0_wen,
input wire [W_DATA-1:0] dbg_data0_rdata,
output wire [W_DATA-1:0] dbg_data0_wdata,
output wire dbg_data0_wen,
// Read port is combinatorial.
// Write port is synchronous, and write effects will be observed on the next clock cycle.
@ -239,6 +239,11 @@ localparam MEIE0 = 12'hbe0; // External interrupt enable register 0
localparam MEIP0 = 12'hfe0; // External interrupt pending register 0
localparam MLEI = 12'hfe4; // Lowest external interrupt number
// ----------------------------------------------------------------------------
// Trigger Module
localparam TSELECT = 12'h7a0;
// ----------------------------------------------------------------------------
// D-mode CSRs
@ -548,21 +553,8 @@ always @ (posedge clk or negedge rst_n) begin
end
end
reg [XLEN-1:0] data0;
always @ (posedge clk or negedge rst_n) begin
if (!rst_n) begin
data0 <= X0;
end else if (DEBUG_SUPPORT) begin
if (dbg_data0_wen)
data0 <= dbg_data0_wdata;
else if (debug_mode && wen && addr == DATA0)
data0 <= update(data0);
end
end
assign dbg_data0_rdata = data0;
assign dbg_data0_wdata = wdata;
assign dbg_data0_wen = wen && addr == DATA0;
// ----------------------------------------------------------------------------
// Read port + detect addressing of unmapped CSRs
@ -811,6 +803,14 @@ always @ (*) begin
rdata = minstreth;
end
// ------------------------------------------------------------------------
// Trigger Module CSRs
TSELECT: if (DEBUG_SUPPORT) begin
decode_match = 1'b1;
// lol
end
// ------------------------------------------------------------------------
// Debug CSRs
@ -840,7 +840,7 @@ always @ (*) begin
DATA0: if (DEBUG_SUPPORT && debug_mode) begin
decode_match = 1'b1;
rdata = data0;
rdata = dbg_data0_rdata;
end
// ------------------------------------------------------------------------