From 5aee830ac00f85f229a99a534352ca5f574c8e21 Mon Sep 17 00:00:00 2001
From: Luke Wren <wren6991@gmail.com>
Date: Fri, 31 Mar 2023 01:53:28 +0100
Subject: [PATCH] Restore SW Makefiles to use whatever riscv32-unknown-elf
 toolchain is in PATH (clean up fallout from Zc implementation -- ensure
 Readme instructions will get you to hello world)

---
 test/sim/common/src_only_app.mk                  | 2 +-
 test/sim/coremark/Makefile                       | 2 +-
 test/sim/coremark/dist/barebones/core_portme.mak | 8 ++++----
 test/sim/dhrystone/Makefile                      | 2 +-
 test/sim/hellow/Makefile                         | 4 ++--
 test/sim/hellow/main.c                           | 4 ----
 test/sim/sw_testcases/Makefile                   | 2 +-
 7 files changed, 10 insertions(+), 14 deletions(-)

diff --git a/test/sim/common/src_only_app.mk b/test/sim/common/src_only_app.mk
index f2e5127..a40f201 100644
--- a/test/sim/common/src_only_app.mk
+++ b/test/sim/common/src_only_app.mk
@@ -8,7 +8,7 @@ endif
 
 CCFLAGS      ?=
 LDSCRIPT     ?= ../common/memmap.ld
-CROSS_PREFIX ?= /opt/riscv/gcc-riscv32-corev/bin/riscv32-corev-elf-
+CROSS_PREFIX ?= riscv32-unknown-elf-
 TBDIR        ?= ../tb_cxxrtl
 INCDIR       ?= ../common
 MAX_CYCLES   ?= 100000
diff --git a/test/sim/coremark/Makefile b/test/sim/coremark/Makefile
index 1c5b230..840fa8c 100644
--- a/test/sim/coremark/Makefile
+++ b/test/sim/coremark/Makefile
@@ -1,7 +1,7 @@
 APP          := coremark
 MAX_CYCLES   := 100000000
 
-CROSS_PREFIX ?= /opt/riscv/gcc-riscv32-corev/bin/riscv32-corev-elf-
+CROSS_PREFIX ?= riscv32-unknown-elf-
 TBDIR        ?= ../tb_cxxrtl
 
 
diff --git a/test/sim/coremark/dist/barebones/core_portme.mak b/test/sim/coremark/dist/barebones/core_portme.mak
index 103c82b..06d0eaf 100755
--- a/test/sim/coremark/dist/barebones/core_portme.mak
+++ b/test/sim/coremark/dist/barebones/core_portme.mak
@@ -19,14 +19,14 @@
 #	Use this flag to define how to to get an executable (e.g -o)
 OUTFLAG= -o
 
-MARCH        = rv32im_zicsr_zba_zbb_zbc_zbs_zca_zcb_zcmp
-CROSS_PREFIX = /opt/riscv/gcc-riscv32-corev/bin/riscv32-corev-elf-
+MARCH        = rv32imac_zicsr_zba_zbb_zbs
+CROSS_PREFIX = riscv32-unknown-elf-
 
 CC           =  $(CROSS_PREFIX)gcc
 LD           =  $(CROSS_PREFIX)gcc
 AS           =  $(CROSS_PREFIX)gcc
 
-PORT_CFLAGS = -O3 -g -march=$(MARCH) -fno-common -funroll-loops -finline-functions --param max-inline-insns-auto=20 -falign-functions=4 -falign-jumps=4 -falign-loops=4
+PORT_CFLAGS = -O3 -g -march=$(MARCH)
 FLAGS_STR = "$(PORT_CFLAGS) $(XCFLAGS) $(XLFLAGS) $(LFLAGS_END)"
 CFLAGS = $(PORT_CFLAGS) -I$(PORT_DIR) -I. -DFLAGS_STR=\"$(FLAGS_STR)\" 
 
@@ -38,7 +38,7 @@ SEPARATE_COMPILE=1
 # You must also define below how to create an object file, and how to link.
 
 OBJOUT 	= -o
-LFLAGS 	= -T ../../common/memmap.ld -Wl,--noinhibit-exec
+LFLAGS 	= -T ../../common/memmap.ld -Wl,--noinhibit-exec -march=$(MARCH)
 ASFLAGS = -c -march=$(MARCH)
 OFLAG 	= -o
 COUT 	= -c
diff --git a/test/sim/dhrystone/Makefile b/test/sim/dhrystone/Makefile
index eb2db86..9e67880 100644
--- a/test/sim/dhrystone/Makefile
+++ b/test/sim/dhrystone/Makefile
@@ -1,6 +1,6 @@
 SRCS       := ../common/init.S src/dhrystone_main.c src/dhrystone.c src/util.c
 APP        := dhrystone
-CCFLAGS    := -O3 -fno-inline -march=rv32im_zicsr
+CCFLAGS    := -O3 -fno-inline -march=rv32im_zicsr_zba_zbb_zbs
 MAX_CYCLES := 1000000
 
 include ../common/src_only_app.mk
diff --git a/test/sim/hellow/Makefile b/test/sim/hellow/Makefile
index a16d1c5..6d706e3 100644
--- a/test/sim/hellow/Makefile
+++ b/test/sim/hellow/Makefile
@@ -1,6 +1,6 @@
 SRCS := ../common/init.S main.c
 APP  := hellow
-CCFLAGS = -march=rv32ima_zicsr_zba_zbb_zbc_zbs_zca_zcb_zcmp -Os
-AFLAGS = -march=rv32ima_zicsr_zba_zbb_zbc_zbs_zca_zcb_zcmp
+CCFLAGS = -march=rv32imac_zicsr_zba_zbb_zbc_zbs -Os
+AFLAGS = -march=rv32imac_zicsr_zba_zbb_zbc_zbs
 
 include ../common/src_only_app.mk
diff --git a/test/sim/hellow/main.c b/test/sim/hellow/main.c
index f3471b4..0546ef5 100644
--- a/test/sim/hellow/main.c
+++ b/test/sim/hellow/main.c
@@ -2,9 +2,5 @@
 
 int main() {
 	tb_puts("Hello world from Hazard3 + CXXRTL!\n");
-	asm volatile(
-		"cm.push {ra, s0-s2}, -16\n"
-		"cm.pop  {ra, s0-s2}, +16\n"
-	);
 	return 123;
 }
diff --git a/test/sim/sw_testcases/Makefile b/test/sim/sw_testcases/Makefile
index 69f5f01..e8cfb65 100644
--- a/test/sim/sw_testcases/Makefile
+++ b/test/sim/sw_testcases/Makefile
@@ -1,6 +1,6 @@
 APP        := hellow
 SRCS        = ../common/init.S $(APP).c $(EXTRA_SRCS_$(APP))
-CCFLAGS    := -march=rv32ima_zicsr_zba_zbb_zbs_zca_zcb_zcmp -Os
+CCFLAGS    := -march=rv32ima_zicsr_zifencei_zba_zbb_zbc_zbs_zbkb -Os
 MAX_CYCLES := 1000000
 INCDIR     := include ../common