From 5d2a562f65a001330aed17bb1dfa1c9882cbd142 Mon Sep 17 00:00:00 2001 From: Luke Wren Date: Thu, 22 Jul 2021 17:30:30 +0100 Subject: [PATCH] Just use read_verilog; write_cxxrtl when building tb_cxxrtl --- test/sim/tb_cxxrtl/Makefile | 2 -- 1 file changed, 2 deletions(-) diff --git a/test/sim/tb_cxxrtl/Makefile b/test/sim/tb_cxxrtl/Makefile index 24ca1e8..2b84bd6 100644 --- a/test/sim/tb_cxxrtl/Makefile +++ b/test/sim/tb_cxxrtl/Makefile @@ -22,8 +22,6 @@ SYNTH_CMD += chparam -set RESET_VECTOR $(CPU_RESET_VECTOR) $(TOP); SYNTH_CMD += chparam -set REDUCED_BYPASS $(REDUCED_BYPASS) $(TOP); SYNTH_CMD += chparam -set MULDIV_UNROLL $(MULDIV_UNROLL) $(TOP); SYNTH_CMD += chparam -set MUL_FAST $(MUL_FAST) $(TOP); -SYNTH_CMD += hierarchy -top $(TOP); proc; opt_clean; -SYNTH_CMD += splitnets -driver; SYNTH_CMD += write_cxxrtl dut.cpp dut.cpp: