From 5dfe5cb62bba2605c9af4a3b7f80a282ba68e348 Mon Sep 17 00:00:00 2001
From: Luke Wren <wren6991@gmail.com>
Date: Wed, 6 Jul 2022 13:49:51 +0100
Subject: [PATCH] Update rvpy to match current fastest config: stage 2 mul,
 single BTB entry on backward branches

---
 test/sim/rvpy/rvpy | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/test/sim/rvpy/rvpy b/test/sim/rvpy/rvpy
index 0aef991..1b43f9a 100755
--- a/test/sim/rvpy/rvpy
+++ b/test/sim/rvpy/rvpy
@@ -162,6 +162,9 @@ class RVCore:
 		self.csr = RVCSR()
 		self.stage3_result = None
 
+		self.btb_valid = False
+		self.btb_pc = 0
+
 	def step(self, instr=None, log=True, cycle_accurate=True):
 		if instr is None:
 			instr = self.mem.mem[self.pc >> 2]
@@ -242,7 +245,6 @@ class RVCore:
 					if funct3 != 0b000:
 						mul_result >>= 32
 					rd_wdata = sext(mul_result, XLEN - 1)
-					stage3_result_next = regnum_rd
 				else:
 					if log:
 						div_instr_name = {0b100: "div", 0b101: "divu", 0b110: "rem", 0b111: "remu"}[funct3]
@@ -344,9 +346,17 @@ class RVCore:
 				instr_invalid = True
 			if not instr_invalid:
 				stall_cycles += regnum_rs1 == self.stage3_result or regnum_rs2 == self.stage3_result
+
+			predicted_taken = self.btb_valid and self.pc == self.btb_pc
+			stall_cycles += taken != predicted_taken
 			if taken:
 				pc_wdata = target
-				stall_cycles += 1
+				if target < self.pc:
+					self.btb_valid = True
+					self.btb_pc = self.pc
+			elif predicted_taken:
+				self.btb_valid = False
+
 
 		elif opc == OPC_LOAD:
 			imm = imm_i(instr)