Add a parameter to control register file reset, instead of the weird ifdef tree

example_soc/soc/example_soc.v

@@ -227,6 +227,7 @@ hazard3_cpu_1port #(
 	.CSR_M_TRAP      (1),
 	.DEBUG_SUPPORT   (1),
 	.NUM_IRQ         (1),
+	.RESET_REGFILE   (0),
 	// Can be overridden from the defaults in hazard3_config.vh during
 	// instantiation of example_soc():
 	.EXTENSION_A     (EXTENSION_A),

hdl/hazard3_config.vh

@@ -129,6 +129,11 @@ parameter MULH_FAST           = 0,
 // especially if Zba extension is enabled. Disabling may save area.
 parameter FAST_BRANCHCMP      = 1,
 
+// RESET_REGFILE: whether to support reset of the general purpose registers.
+// There are around 1k bits in the register file, so the reset can be
+// disabled e.g. to permit block-RAM inference on FPGA.
+parameter RESET_REGFILE       = 1,
+
 // MTVEC_WMASK: Mask of which bits in MTVEC are modifiable. Save gates by
 // making trap vector base partly fixed (legal, as it's WARL).
 //

hdl/hazard3_config_inst.vh

@@ -33,5 +33,6 @@
 .MULH_FAST          (MULH_FAST),
 .FAST_BRANCHCMP     (FAST_BRANCHCMP),
 .MTVEC_WMASK        (MTVEC_WMASK),
+.RESET_REGFILE      (RESET_REGFILE),
 .W_ADDR             (W_ADDR),
 .W_DATA             (W_DATA)

hdl/hazard3_core.v

@@ -1032,19 +1032,10 @@ end
 
 
 hazard3_regfile_1w2r #(
-	.FAKE_DUALPORT(0),
-`ifdef SIM
-	.RESET_REGS(1),
-`elsif FORMAL
-	.RESET_REGS(1),
-`elsif FPGA
-	.RESET_REGS(0),
-`else
-	.RESET_REGS(1),
-`endif
-	.N_REGS(32),
-	.W_DATA(W_DATA)
-) inst_regfile_1w2r (
+	.RESET_REGS (RESET_REGFILE),
+	.N_REGS     (32),
+	.W_DATA     (W_DATA)
+) regs (
 	.clk    (clk),
 	.rst_n  (rst_n),
 	// On downstream stall, we feed D's addresses back into regfile