colin
/
Hazard3
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Remove flash XIP from example_soc -- keep it simple and reclaim UART FTDI pins on iCEBreaker

This commit is contained in:
Luke Wren 2021-11-21 15:55:52 +00:00
parent ba9a7b4a03
commit 60f364e561
4 changed files with 39 additions and 178 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Readme.md
View File

@ -46,7 +46,7 @@ This is essentially Hazard5, with the `D` and `X` stages merged and the register
# Cloning This Repository # Cloning This Repository
For the purpose of running hello world, or using Hazard3 in your design, this repository is self-contained. You will need to pull in the submodules for compliance tests and for components for the example SoC: For the purpose of using Hazard3 in your design, this repository is self-contained. You will need to pull in the submodules for simulation scripts, compliance tests and for components for the example SoC:
```bash ```bash
git clone --recursive https://github.com/Wren6991/Hazard3.git hazard3 git clone --recursive https://github.com/Wren6991/Hazard3.git hazard3

17
example_soc/fpga/fpga_icebreaker.v
View File

@ -37,13 +37,7 @@ module fpga_icebreaker (
output wire mirror_tdo, output wire mirror_tdo,
output wire uart_tx, output wire uart_tx,
input wire uart_rx, input wire uart_rx
output wire spi_cs_n,
output wire spi_sck,
output wire spi_mosi,
input wire spi_miso
); );
assign mirror_tck = tck; assign mirror_tck = tck;
@ -82,7 +76,7 @@ activity_led #(
example_soc #( example_soc #(
.MUL_FAST (1), .MUL_FAST (1),
.EXTENSION_C (0), .EXTENSION_C (0),
.CSR_COUNTER (0) .CSR_COUNTER (1)
) soc_u ( ) soc_u (
.clk (clk_sys), .clk (clk_sys),
.rst_n (rst_n_sys), .rst_n (rst_n_sys),
@ -94,12 +88,7 @@ example_soc #(
.tdo (tdo), .tdo (tdo),
.uart_tx (uart_tx), .uart_tx (uart_tx),
.uart_rx (uart_rx), .uart_rx (uart_rx)
.spi_cs_n (spi_cs_n),
.spi_sck (spi_sck),
.spi_mosi (spi_mosi),
.spi_miso (spi_miso)
); );
endmodule endmodule

180
example_soc/soc/example_soc.v
View File

@ -39,12 +39,7 @@ module example_soc #(
// IO // IO
output wire uart_tx, output wire uart_tx,
input wire uart_rx, input wire uart_rx
output wire spi_cs_n,
output wire spi_sck,
output wire spi_mosi,
input wire spi_miso
); );
localparam W_ADDR = 32; localparam W_ADDR = 32;
@ -63,7 +58,7 @@ wire dmi_pready;
wire dmi_pslverr; wire dmi_pslverr;
// TCK-domain DTM logic can force a hard reset of the // TCK-domain DTM logic can force a hard reset
wire dmihardreset_req; wire dmihardreset_req;
wire assert_dmi_reset = !rst_n || dmihardreset_req; wire assert_dmi_reset = !rst_n || dmihardreset_req;
wire rst_n_dmi; wire rst_n_dmi;
@ -300,8 +295,6 @@ hazard3_cpu_1port #(
// - 128 kB SRAM at... 0x0000_0000 // - 128 kB SRAM at... 0x0000_0000
// - System timer at.. 0x4000_0000 // - System timer at.. 0x4000_0000
// - UART at.......... 0x4000_4000 // - UART at.......... 0x4000_4000
// - XIP controls at.. 0x4000_8000
// - XIP window at.... 0x8000_0000
// AHBL layer // AHBL layer
@ -331,27 +324,13 @@ wire bridge_hmastlock;
wire [W_DATA-1:0] bridge_hwdata; wire [W_DATA-1:0] bridge_hwdata;
wire [W_DATA-1:0] bridge_hrdata; wire [W_DATA-1:0] bridge_hrdata;
wire xip_hready_resp;
wire xip_hready;
wire xip_hresp;
wire [W_ADDR-1:0] xip_haddr;
wire xip_hwrite;
wire [1:0] xip_htrans;
wire [2:0] xip_hsize;
wire [2:0] xip_hburst;
wire [3:0] xip_hprot;
wire xip_hmastlock;
wire [W_DATA-1:0] xip_hwdata;
wire [W_DATA-1:0] xip_hrdata;
ahbl_splitter #( ahbl_splitter #(
.N_PORTS (3), .N_PORTS (2),
.ADDR_MAP (96'h80000000_40000000_00000000), .ADDR_MAP (64'h40000000_00000000),
.ADDR_MASK (96'he0000000_e0000000_e0000000) .ADDR_MASK (64'he0000000_e0000000)
) splitter_u ( ) splitter_u (
.clk (clk), .clk (clk),
.rst_n (rst_n), .rst_n (rst_n),
.src_hready_resp (proc_hready ), .src_hready_resp (proc_hready ),
.src_hready (proc_hready ), .src_hready (proc_hready ),
@ -366,18 +345,18 @@ ahbl_splitter #(
.src_hwdata (proc_hwdata ), .src_hwdata (proc_hwdata ),
.src_hrdata (proc_hrdata ), .src_hrdata (proc_hrdata ),
.dst_hready_resp ({xip_hready_resp , bridge_hready_resp , sram0_hready_resp}), .dst_hready_resp ({bridge_hready_resp , sram0_hready_resp}),
.dst_hready ({xip_hready , bridge_hready , sram0_hready }), .dst_hready ({bridge_hready , sram0_hready }),
.dst_hresp ({xip_hresp , bridge_hresp , sram0_hresp }), .dst_hresp ({bridge_hresp , sram0_hresp }),
.dst_haddr ({xip_haddr , bridge_haddr , sram0_haddr }), .dst_haddr ({bridge_haddr , sram0_haddr }),
.dst_hwrite ({xip_hwrite , bridge_hwrite , sram0_hwrite }), .dst_hwrite ({bridge_hwrite , sram0_hwrite }),
.dst_htrans ({xip_htrans , bridge_htrans , sram0_htrans }), .dst_htrans ({bridge_htrans , sram0_htrans }),
.dst_hsize ({xip_hsize , bridge_hsize , sram0_hsize }), .dst_hsize ({bridge_hsize , sram0_hsize }),
.dst_hburst ({xip_hburst , bridge_hburst , sram0_hburst }), .dst_hburst ({bridge_hburst , sram0_hburst }),
.dst_hprot ({xip_hprot , bridge_hprot , sram0_hprot }), .dst_hprot ({bridge_hprot , sram0_hprot }),
.dst_hmastlock ({xip_hmastlock , bridge_hmastlock , sram0_hmastlock }), .dst_hmastlock ({bridge_hmastlock , sram0_hmastlock }),
.dst_hwdata ({xip_hwdata , bridge_hwdata , sram0_hwdata }), .dst_hwdata ({bridge_hwdata , sram0_hwdata }),
.dst_hrdata ({xip_hrdata , bridge_hrdata , sram0_hrdata }) .dst_hrdata ({bridge_hrdata , sram0_hrdata })
); );
// APB layer // APB layer
@ -409,16 +388,6 @@ wire [31:0] timer_prdata;
wire timer_pready; wire timer_pready;
wire timer_pslverr; wire timer_pslverr;
wire xip_psel;
wire xip_penable;
wire xip_pwrite;
wire [15:0] xip_paddr;
wire [31:0] xip_pwdata;
wire [31:0] xip_prdata;
wire xip_pready;
wire xip_pslverr;
ahbl_to_apb apb_bridge_u ( ahbl_to_apb apb_bridge_u (
.clk (clk), .clk (clk),
.rst_n (rst_n), .rst_n (rst_n),
@ -447,9 +416,9 @@ ahbl_to_apb apb_bridge_u (
); );
apb_splitter #( apb_splitter #(
.N_SLAVES (3), .N_SLAVES (2),
.ADDR_MAP (48'h8000_4000_0000), .ADDR_MAP (32'h4000_0000),
.ADDR_MASK (48'hc000_c000_c000) .ADDR_MASK (32'hc000_c000)
) inst_apb_splitter ( ) inst_apb_splitter (
.apbs_paddr (bridge_paddr), .apbs_paddr (bridge_paddr),
.apbs_psel (bridge_psel), .apbs_psel (bridge_psel),
@ -460,14 +429,14 @@ apb_splitter #(
.apbs_prdata (bridge_prdata), .apbs_prdata (bridge_prdata),
.apbs_pslverr (bridge_pslverr), .apbs_pslverr (bridge_pslverr),
.apbm_paddr ({xip_paddr , uart_paddr , timer_paddr }), .apbm_paddr ({uart_paddr , timer_paddr }),
.apbm_psel ({xip_psel , uart_psel , timer_psel }), .apbm_psel ({uart_psel , timer_psel }),
.apbm_penable ({xip_penable , uart_penable , timer_penable}), .apbm_penable ({uart_penable , timer_penable}),
.apbm_pwrite ({xip_pwrite , uart_pwrite , timer_pwrite }), .apbm_pwrite ({uart_pwrite , timer_pwrite }),
.apbm_pwdata ({xip_pwdata , uart_pwdata , timer_pwdata }), .apbm_pwdata ({uart_pwdata , timer_pwdata }),
.apbm_pready ({xip_pready , uart_pready , timer_pready }), .apbm_pready ({uart_pready , timer_pready }),
.apbm_prdata ({xip_prdata , uart_prdata , timer_prdata }), .apbm_prdata ({uart_prdata , timer_prdata }),
.apbm_pslverr ({xip_pslverr , uart_pslverr , timer_pslverr}) .apbm_pslverr ({uart_pslverr , timer_pslverr})
); );
// ---------------------------------------------------------------------------- // ----------------------------------------------------------------------------
@ -489,7 +458,7 @@ ahb_sync_sram #(
.ahbls_haddr (sram0_haddr), .ahbls_haddr (sram0_haddr),
.ahbls_hwrite (sram0_hwrite), .ahbls_hwrite (sram0_hwrite),
.ahbls_htrans (sram0_htrans), .ahbls_htrans (sram0_htrans),
.ahbls_hsize (sram0_hsize), .ahbls_hsize (sram0_hsize),
.ahbls_hburst (sram0_hburst), .ahbls_hburst (sram0_hburst),
.ahbls_hprot (sram0_hprot), .ahbls_hprot (sram0_hprot),
.ahbls_hmastlock (sram0_hmastlock), .ahbls_hmastlock (sram0_hmastlock),
@ -539,91 +508,4 @@ hazard3_riscv_timer timer_u (
.timer_irq (timer_irq) .timer_irq (timer_irq)
); );
wire xip_uncached_hready_resp;
wire xip_uncached_hready;
wire xip_uncached_hresp;
wire [23:0] xip_uncached_haddr;
wire xip_uncached_hwrite;
wire [1:0] xip_uncached_htrans;
wire [2:0] xip_uncached_hsize;
wire [2:0] xip_uncached_hburst;
wire [3:0] xip_uncached_hprot;
wire xip_uncached_hmastlock;
wire [W_DATA-1:0] xip_uncached_hwdata;
wire [W_DATA-1:0] xip_uncached_hrdata;
ahb_cache_readonly #(
.N_WAYS (1),
.W_ADDR (24),
.W_DATA (32),
.W_LINE (32),
.TMEM_PRELOAD (""),
.DMEM_PRELOAD (""),
// 4 kB cache, 12 iCE40 BRAMs (1024 x 32 data, 1024 x (12 + 1) (tag + valid))
.DEPTH (1024)
) xip_cache_u (
.clk (clk),
.rst_n (rst_n),
.src_hready_resp (xip_hready_resp),
.src_hready (xip_hready),
.src_hresp (xip_hresp),
.src_haddr (xip_haddr[23:0]),
.src_hwrite (xip_hwrite),
.src_htrans (xip_htrans),
.src_hsize (xip_hsize),
.src_hburst (xip_hburst),
.src_hprot (xip_hprot),
.src_hmastlock (xip_hmastlock),
.src_hwdata (xip_hwdata),
.src_hrdata (xip_hrdata),
.dst_hready_resp (xip_uncached_hready_resp),
.dst_hready (xip_uncached_hready),
.dst_hresp (xip_uncached_hresp),
.dst_haddr (xip_uncached_haddr),
.dst_hwrite (xip_uncached_hwrite),
.dst_htrans (xip_uncached_htrans),
.dst_hsize (xip_uncached_hsize),
.dst_hburst (xip_uncached_hburst),
.dst_hprot (xip_uncached_hprot),
.dst_hmastlock (xip_uncached_hmastlock),
.dst_hwdata (xip_uncached_hwdata),
.dst_hrdata (xip_uncached_hrdata)
);
spi_03h_xip xip_u (
.clk (clk),
.rst_n (rst_n),
.apbs_psel (xip_psel),
.apbs_penable (xip_penable),
.apbs_pwrite (xip_pwrite),
.apbs_paddr (xip_paddr),
.apbs_pwdata (xip_pwdata),
.apbs_prdata (xip_prdata),
.apbs_pready (xip_pready),
.apbs_pslverr (xip_pslverr),
.ahbls_hready_resp (xip_uncached_hready_resp),
.ahbls_hready (xip_uncached_hready),
.ahbls_hresp (xip_uncached_hresp),
.ahbls_haddr (xip_uncached_haddr),
.ahbls_hwrite (xip_uncached_hwrite),
.ahbls_htrans (xip_uncached_htrans),
.ahbls_hsize (xip_uncached_hsize),
.ahbls_hburst (xip_uncached_hburst),
.ahbls_hprot (xip_uncached_hprot),
.ahbls_hmastlock (xip_uncached_hmastlock),
.ahbls_hwdata (xip_uncached_hwdata),
.ahbls_hrdata (xip_uncached_hrdata),
.spi_cs_n (spi_cs_n),
.spi_sck (spi_sck),
.spi_mosi (spi_mosi),
.spi_miso (spi_miso)
);
endmodule endmodule

18
example_soc/synth/fpga_icebreaker.pcf
View File

@ -15,23 +15,13 @@ set_io tdi 9 # FTDI BDBUS1
set_io tdo 18 # FTDI BDBUS2 set_io tdo 18 # FTDI BDBUS2
set_io tms 19 # FTDI BDBUS3 set_io tms 19 # FTDI BDBUS3
# # UART is moved over to FTDI A channel -- this means flash is inaccessible # UART is moved over to FTDI A channel -- this means flash is inaccessible
# # (and stays in a quiescent state since CSn is disconnected and pulled high) # (and stays in a quiescent state since CSn is disconnected and pulled high)
# set_io uart_rx 15 # FTDI ADBUS0, flash SCK, iCE SCK set_io uart_rx 15 # FTDI ADBUS0, flash SCK, iCE SCK
# set_io uart_tx 14 # FTDI ADBUS1, flash MOSI, iCE SO (if jumper J15 connected) set_io uart_tx 14 # FTDI ADBUS1, flash MOSI, iCE SO (if jumper J15 connected)
# FIXME UART clashes with SPI signals, so punt it onto a header
set_io uart_rx 4 # P1A1
set_io uart_tx 2 # P1A2
set_io led 37 # Green on main board set_io led 37 # Green on main board
# SPI flash
set_io spi_mosi 14
set_io spi_miso 17
set_io spi_sck 15
set_io spi_cs_n 16
# # Buttons # # Buttons
# set_io dpad_u 20 # Snapoff top # set_io dpad_u 20 # Snapoff top
# set_io dpad_d 18 # Snapoff bottom # set_io dpad_d 18 # Snapoff bottom