More work on traps, delaying IRQs which arrive whilst a load/store address phase is stalled to avoid deassertion on the bus
This commit is contained in:
Luke Wren
parent
1b252d4bda
commit
65075df0e5
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@ -1,3 +1,6 @@
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file hazard3_core.v
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file hazard3_cpu_1port.v
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file hazard3_cpu_2port.v
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file arith/hazard3_alu.v
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file arith/hazard3_shift_barrel.v
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file arith/hazard3_priority_encode.v
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@ -8,7 +11,4 @@ file hazard3_instr_decompress.v
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file hazard3_decode.v
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file hazard3_csr.v
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file hazard3_regfile_1w2r.v
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file hazard3_core.v
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file hazard3_cpu_1port.v
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file hazard3_cpu_2port.v
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include .
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@ -2,7 +2,7 @@
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* DO WHAT THE FUCK YOU WANT TO AND DON'T BLAME US PUBLIC LICENSE *
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* Version 3, April 2008 *
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* *
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* Copyright (C) 2018 Luke Wren *
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* Copyright (C) 2021 Luke Wren *
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* *
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* Everyone is permitted to copy and distribute verbatim or modified *
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* copies of this license document and accompanying software, and *
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@ -15,6 +15,8 @@
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* *
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*********************************************************************/
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`default_nettype none
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module hazard3_core #(
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`include "hazard3_config.vh"
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,
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@ -221,6 +223,7 @@ wire [W_DATA-1:0] x_alu_add;
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wire x_alu_cmp;
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wire [W_DATA-1:0] m_trap_addr;
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wire m_trap_is_irq;
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wire m_trap_enter_vld;
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wire m_trap_enter_rdy = f_jump_rdy;
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@ -231,6 +234,8 @@ reg [W_DATA-1:0] xm_result;
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reg [W_DATA-1:0] xm_store_data;
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reg [W_MEMOP-1:0] xm_memop;
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reg [W_EXCEPT-1:0] xm_except;
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reg xm_delay_irq_entry;
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reg x_stall_raw;
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wire x_stall_muldiv;
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@ -326,7 +331,7 @@ always @ (*) begin
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MEMOP_SH: bus_hsize_d = HSIZE_HWORD;
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default: bus_hsize_d = HSIZE_BYTE;
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endcase
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bus_aph_req_d = x_memop_vld && !(x_stall_raw || m_trap_enter_vld);
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bus_aph_req_d = x_memop_vld && !(x_stall_raw || x_unaligned_addr || m_trap_enter_vld);
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end
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// Multiply/divide
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@ -435,9 +440,17 @@ reg prev_instr_was_32_bit;
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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xm_delay_irq_entry <= 1'b0;
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prev_instr_was_32_bit <= 1'b0;
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end else if (!x_stall) begin
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prev_instr_was_32_bit <= df_cir_use == 2'd2;
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end else begin
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// Must hold off IRQ if we are in the second cycle of an address phase or
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// later, since at that point the load/store can't be revoked. The IRQ is
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// taken once this load/store moves to the next stage: if another load/store
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// is chasing down the pipeline then this is immediately suppressed by the
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// IRQ entry, before its address phase can begin.
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xm_delay_irq_entry <= bus_aph_req_d && !bus_aph_ready_d;
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if (!x_stall)
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prev_instr_was_32_bit <= df_cir_use == 2'd2;
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end
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end
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@ -447,6 +460,7 @@ hazard3_csr #(
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) inst_hazard3_csr (
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.clk (clk),
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.rst_n (rst_n),
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// CSR access port
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// *en_soon are early access strobes which are not a function of bus stall.
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// Can generate access faults (hence traps), but do not actually perform access.
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@ -459,14 +473,19 @@ hazard3_csr #(
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.ren_soon (d_csr_ren && !m_trap_enter_vld),
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.ren (d_csr_ren && !m_trap_enter_vld && !x_stall),
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.illegal (x_csr_illegal_access),
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// Trap signalling
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.trap_addr (m_trap_addr),
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.trap_is_irq (m_trap_is_irq),
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.trap_enter_vld (m_trap_enter_vld),
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.trap_enter_rdy (m_trap_enter_rdy),
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.mepc_in (d_pc - (prev_instr_was_32_bit ? 32'h4 : 32'h2)),
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// IRQ and exception requests
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.delay_irq_entry (xm_delay_irq_entry),
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.irq (irq),
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.except (xm_except),
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// Other CSR-specific signalling
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.instr_ret (|df_cir_use)
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);
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@ -488,7 +507,7 @@ always @ (posedge clk or negedge rst_n) begin
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{xm_rs1, xm_rs2, xm_rd} <= {d_rs1, d_rs2, d_rd};
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// If the transfer is unaligned, make sure it is completely NOP'd on the bus
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xm_memop <= d_memop | {x_unaligned_addr, 3'h0};
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if (x_stall || m_trap_enter_vld) begin
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if (x_stall || m_trap_enter_vld && () begin
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// Insert bubble
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xm_rd <= {W_REGADDR{1'b0}};
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xm_memop <= MEMOP_NONE;
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@ -2,7 +2,7 @@
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* DO WHAT THE FUCK YOU WANT TO AND DON'T BLAME US PUBLIC LICENSE *
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* Version 3, April 2008 *
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* *
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* Copyright (C) 2019 Luke Wren *
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* Copyright (C) 2021 Luke Wren *
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* *
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* Everyone is permitted to copy and distribute verbatim or modified *
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* copies of this license document and accompanying software, and *
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@ -15,6 +15,8 @@
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* *
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*****************************************************************************/
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`default_nettype none
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// Control and Status Registers (CSRs)
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// Also includes CSR-related logic like interrupt enable/masking,
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// trap vector calculation.
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@ -62,11 +64,13 @@ module hazard3_csr #(
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// Note that an exception input can go away, e.g. if the pipe gets flushed. In this
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// case we lower trap_enter_vld.
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output wire [XLEN-1:0] trap_addr,
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output wire trap_is_irq,
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output wire trap_enter_vld,
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input wire trap_enter_rdy,
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input wire [XLEN-1:0] mepc_in,
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// Exceptions must *not* be a function of bus stall.
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input wire delay_irq_entry,
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input wire [15:0] irq,
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input wire [W_EXCEPT-1:0] except,
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@ -292,7 +296,6 @@ end
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// Exception program counter
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reg [XLEN-1:0] mepc;
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assign mepc_out = mepc;
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// LSB is always 0
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localparam MEPC_MASK = {{XLEN-1{1'b1}}, 1'b0};
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@ -678,7 +681,7 @@ assign mip = {
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// We don't actually trap the aggregate IRQ, just provide it for software info
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wire [31:0] mip_no_global = mip & 32'hffff_f7ff;
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wire irq_any = |(mip_no_global & {{16{mie_meie}}, {16{1'b1}}}) && mstatus_mie;
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wire irq_any = |(mip_no_global & {{16{mie_meie}}, {16{1'b1}}}) && mstatus_mie && !delay_irq_entry;
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wire [4:0] irq_num;
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hazard3_priority_encode #(
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@ -694,10 +697,11 @@ wire [11:0] mtvec_offs = (exception_req_any ?
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) << 2;
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assign trap_addr = except == EXCEPT_MRET ? mepc : mtvec | {20'h0, mtvec_offs};
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assign trap_is_irq = !exception_req_any;
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assign trap_enter_vld = CSR_M_TRAP && (exception_req_any || irq_any);
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assign mcause_irq_next = !exception_req_any;
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assign mcause_code_next = exception_req_any ? exception_req_num : {1'b0, irq_num};
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assign mcause_code_next = exception_req_any ? except : {1'b0, irq_num};
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// ----------------------------------------------------------------------------
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@ -15,6 +15,8 @@
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* *
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*****************************************************************************/
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`default_nettype none
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module hazard3_decode #(
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`include "hazard3_config.vh"
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,
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@ -106,7 +108,7 @@ assign df_cir_use =
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// Note that it is not possible to simply gate the jump request based on X stalling,
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// because X stall is a function of hready, and jump request feeds haddr htrans etc.
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wire jump_caused_by_d = f_jump_now && x_jump_from_instr;
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wire jump_caused_by_d = f_jump_now && x_jump_not_except;
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wire assert_cir_lock = jump_caused_by_d && d_stall;
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wire deassert_cir_lock = !d_stall;
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reg cir_lock_prev;
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@ -1,3 +1,22 @@
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/******************************************************************************
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* DO WHAT THE FUCK YOU WANT TO AND DON'T BLAME US PUBLIC LICENSE *
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* Version 3, April 2008 *
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* *
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* Copyright (C) 2021 Luke Wren *
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* *
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* Everyone is permitted to copy and distribute verbatim or modified *
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* copies of this license document and accompanying software, and *
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* changing either is allowed. *
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* *
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* TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION *
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* *
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* 0. You just DO WHAT THE FUCK YOU WANT TO. *
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* 1. We're NOT RESPONSIBLE WHEN IT DOESN'T FUCKING WORK. *
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* *
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*****************************************************************************/
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`default_nettype none
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module hazard3_frontend #(
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parameter FIFO_DEPTH = 2, // power of 2, >= 1
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`include "hazard3_config.vh"
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@ -170,7 +189,7 @@ always @ (posedge clk or negedge rst_n) begin
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unaligned_jump_aph <= 1'b0;
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unaligned_jump_dph <= 1'b0;
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end else if (EXTENSION_C) begin
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`ifdef FORMAL
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`ifdef FORMAL_FIXMEEEE
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assert(!(unaligned_jump_aph && !unaligned_jump_dph));
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assert(!($past(jump_now && !jump_target[1]) && unaligned_jump_aph));
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assert(!($past(jump_now && !jump_target[1]) && unaligned_jump_dph));
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@ -276,9 +295,8 @@ always @ (posedge clk or negedge rst_n) begin
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end else begin
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`ifdef FORMAL
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assert(cir_vld <= 2);
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assert(cir_use <= 2);
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assert(cir_use <= cir_vld);
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assert(cir_vld <= buf_level || $past(cir_lock));
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// assert(cir_vld <= buf_level || $past(cir_lock));
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`endif
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// Update CIR flags
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buf_level <= buf_level_next;
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@ -1,7 +1,7 @@
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// ----------------------------------------------------------------------------
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// RVFI Instrumentation
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// ----------------------------------------------------------------------------
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// To be included into hazard3_cpu.v for use with riscv-formal.
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// To be included into hazard3_core.v for use with riscv-formal.
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// Contains some state modelling to diagnose exactly what the core is doing,
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// and report this in a way RVFI understands.
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// We consider instructions to "retire" as they cross the M/W pipe register.
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@ -21,8 +21,7 @@ wire rvfm_x_valid = fd_cir_vld >= 2 || (fd_cir_vld >= 1 && fd_cir[1:0] != 2'b11)
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reg rvfm_m_valid;
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reg [31:0] rvfm_m_instr;
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wire rvfm_x_trap = x_trap_is_exception && x_trap_enter;
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reg rvfm_m_trap;
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wire rvfm_m_trap = xm_except != EXCEPT_NONE && xm_except != EXCEPT_MRET && m_trap_enter_rdy;
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reg rvfm_entered_intr;
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reg rvfi_valid_r;
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@ -36,21 +35,21 @@ assign rvfi_trap = rvfi_trap_r;
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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rvfm_m_valid <= 1'b0;
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rvfm_m_trap <= 1'b0;
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rvfm_entered_intr <= 1'b0;
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rvfi_valid_r <= 1'b0;
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rvfi_trap_r <= 1'b0;
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rvfi_insn_r <= 32'h0;
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end else begin
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if (!x_stall) begin
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// Squash X instrs on IRQ entry -- these instructions will be reexecuted on return.
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rvfm_m_valid <= |df_cir_use && !(x_trap_enter && x_trap_enter_rdy && !rvfm_x_trap);
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// X instruction squashed by any trap, as it's in the branch shadow
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rvfm_m_valid <= |df_cir_use && !m_trap_enter_vld;
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rvfm_m_instr <= {fd_cir[31:16] & {16{df_cir_use[1]}}, fd_cir[15:0]};
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rvfm_m_trap <= rvfm_x_trap;
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end else if (!m_stall) begin
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rvfm_m_valid <= 1'b0;
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end
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rvfi_valid_r <= rvfm_m_valid && !m_stall;
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// Squash instructions where an IRQ is taken (but keep instructions which
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// cause an exception... which is really what the rvfi_trap signal refers to)
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rvfi_valid_r <= rvfm_m_valid && !m_stall && !(m_trap_enter_vld && !rvfm_m_trap);
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rvfi_insn_r <= rvfm_m_instr;
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rvfi_trap_r <= rvfm_m_trap;
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@ -93,13 +92,12 @@ always @ (posedge clk or negedge rst_n)
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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rvfm_dx_have_jumped <= 0;
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rvfm_xm_pc <= 0;
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rvfm_xm_pc_next <= 0;
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end else begin
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if (!x_stall) begin
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rvfm_xm_pc <= d_pc;
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rvfm_xm_pc_next <= f_jump_now || rvfm_past_df_cir_lock ? x_jump_target : d_mispredict_addr;
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rvfm_xm_pc_next <= f_jump_now || rvfm_past_df_cir_lock ? x_jump_target : d_pc + (fd_cir[1:0] == 2'b11 ? 32'h4 : 32'h2);
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end
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end
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end
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@ -16,7 +16,7 @@ module rvfi_wrapper (
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(* keep *) wire [3:0] i_hprot;
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(* keep *) wire i_hmastlock;
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(* keep *) `rvformal_rand_reg i_hready;
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(* keep *) wire i_hresp;
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(* keep *) `rvformal_rand_reg i_hresp;
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(* keep *) wire [31:0] i_hwdata;
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(* keep *) `rvformal_rand_reg [31:0] i_hrdata;
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@ -28,7 +28,7 @@ module rvfi_wrapper (
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(* keep *) wire [3:0] d_hprot;
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(* keep *) wire d_hmastlock;
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(* keep *) `rvformal_rand_reg d_hready;
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(* keep *) wire d_hresp;
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(* keep *) `rvformal_rand_reg d_hresp;
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(* keep *) wire [31:0] d_hwdata;
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(* keep *) `rvformal_rand_reg [31:0] d_hrdata;
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