Add A bit to MISA, update docs

doc/sections/csr.adoc

@@ -85,6 +85,7 @@ Read-only, constant. Value depends on which ISA extensions Hazard3 is configured
 | 23 | `x` | 1 if the core is configured to support trap-handling, otherwise 0. Hazard3 has nonstandard CSRs to enable/disable external interrupts on a per-interrupt basis, see <<reg-meie0>> and <<reg-meip0>>. The `misa.x` bit must be set to indicate their presence. Hazard3 does not implement any custom instructions.
 | 12 | `m` | 1 if the M extension is present, otherwise 0.
 | 2 | `c` | 1 if the C extension is present, otherwise 0.
+| 0 | `a` | 1 if the A extension is present, otherwise 0.
 |===
 
 === Standard M-mode Trap Handling CSRs

doc/sections/instruction_timings.adoc

@@ -94,7 +94,7 @@ Timings assume the core is configured with `MULDIV_UNROLL = 2` and `MUL_FAST = 1
 
 === C Extension
 
-All C extension 16-bit instructions on Hazard3 are aliases of base RV32I instructions. They perform identically to their 32-bit counterparts.
+All C extension 16-bit instructions are aliases of base RV32I instructions. On Hazard3, they perform identically to their 32-bit counterparts.
 
 A consequence of the C extension is that 32-bit instructions can be non-naturally-aligned. This has no penalty during sequential execution, but branching to a 32-bit instruction that is not 32-bit-aligned carries a 1 cycle penalty, because the instruction fetch is cracked into two naturally-aligned bus accesses.
 

doc/sections/introduction.adoc

@@ -4,6 +4,7 @@ Hazard3 is a 3-stage RISC-V processor, providing the following architectural sup
 
 * `RV32I`: 32-bit base instruction set
 * `M`: integer multiply/divide/modulo
+* `A`: atomic memory operations
 * `C`: compressed instructions
 * `Zba`: address generation
 * `Zbb`: basic bit manipulation
@@ -17,8 +18,5 @@ Hazard3 is a 3-stage RISC-V processor, providing the following architectural sup
 
 The following are planned for future implementation:
 
-* `A` extension: atomic memory access
-** `LR`/`SC` fully supported
-** AMONone PMA on all of memory (AMOs are decoded but unconditionally trigger access fault without attempting memory access)
 * Trigger unit for debug mode
 ** Likely breakpoints only

hdl/hazard3_csr.v

@@ -576,7 +576,8 @@ always @ (*) begin
 			1'b1,              // Integer ISA
 			5'd0,              // H...D, no
 			|EXTENSION_C,
-			2'b0
+			1'b0,
+			|EXTENSION_A
 		};
 	end
 	MVENDORID: if (CSR_M_MANDATORY) begin