diff --git a/example_soc/icebreaker-openocd.cfg b/example_soc/icebreaker-openocd.cfg
index 3620010..9b46db0 100644
--- a/example_soc/icebreaker-openocd.cfg
+++ b/example_soc/icebreaker-openocd.cfg
@@ -1,8 +1,8 @@
 adapter driver ftdi
 
 # 30 MHz -- a bit exciting but it seems reliable
-adapter speed 3000
-# ftdi_tdo_sample_edge falling
+adapter speed 30000
+ftdi_tdo_sample_edge falling
 
 # JTAG is on FTDI B channel so it doesn't inadvertently assert flash CS pin
 # (usually UART would be on the B channel).
diff --git a/example_soc/soc/example_soc.v b/example_soc/soc/example_soc.v
index 8fb02fc..1855323 100644
--- a/example_soc/soc/example_soc.v
+++ b/example_soc/soc/example_soc.v
@@ -327,7 +327,7 @@ wire [W_DATA-1:0]  bridge_hrdata;
 
 ahbl_splitter #(
 	.N_PORTS     (2),
-	.ADDR_MAP    (64'h40000000_20000000),
+	.ADDR_MAP    (64'h40000000_00000000),
 	.ADDR_MASK   (64'he0000000_e0000000)
 ) splitter_u (
 	.clk (clk),
diff --git a/hdl/debug/dtm/hazard3_ecp5_jtag_dtm.v b/hdl/debug/dtm/hazard3_ecp5_jtag_dtm.v
index afe747f..ff7ff2c 100644
--- a/hdl/debug/dtm/hazard3_ecp5_jtag_dtm.v
+++ b/hdl/debug/dtm/hazard3_ecp5_jtag_dtm.v
@@ -115,23 +115,14 @@ always @ (posedge jtck or negedge jrst_n) begin
         core_dr_ren <= 1'b0;
         dr_shift_en <= 1'b0;
     end else begin
-        core_dr_sel_dmi_ndtmcs <= jce1 ? 1'b0 : jce2 ? 1'b1 : dr_sel_prev;
+        if (jce1 || jce2)
+            core_dr_sel_dmi_ndtmcs <= jce2;
         core_dr_ren <= (jce1 || jce2) && !jshift;
         core_dr_wen <= jupdate;
         dr_shift_en <= jshift;
     end
 end
 
-reg dr_sel_prev;
-
-always @ (posedge jtck or negedge jrst_n) begin
-    if (!jrst_n) begin
-        dr_sel_prev <= 1'b0;
-    end else begin
-        dr_sel_prev <= core_dr_sel_dmi_ndtmcs;
-    end
-end
-
 reg [W_DR_SHIFT-1:0] dr_shift;
 assign core_dr_wdata = dr_shift;