Add PMP U-mode read/write permission test
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Luke Wren
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c8afcdbb8f
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71eff7649d
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#include "tb_cxxrtl_io.h"
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#include "hazard3_csr.h"
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#include "pmp.h"
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// Check that PMP correctly controls U-mode R/W permissions, for all three
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// access sizes.
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#define MCAUSE_LOAD_FAULT 5
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#define MCAUSE_STORE_FAULT 7
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#define MCAUSE_ECALL_UMODE 8
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/*EXPECTED-OUTPUT***************************************************************
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Initial word read/write check
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mcause = 8
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mcause = 8
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Remove read permission, word read/write
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mcause = 8
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mcause = 5
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Restore read permission, remove write permission, word read/write
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mcause = 7
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mcause = 8
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Remove read permission, halfword read/write
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mcause = 8
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mcause = 5
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Restore read permission, remove write permission, halfword read/write
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mcause = 7
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mcause = 8
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Remove read permission, byte read/write
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mcause = 8
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mcause = 5
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Restore read permission, remove write permission, byte read/write
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mcause = 7
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mcause = 8
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*******************************************************************************/
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typedef uint32_t uxlen_t;
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typedef uxlen_t (*umode_func_2a_1r)(uxlen_t, uxlen_t);
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// /!\ Unconventional control flow ahead
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// Call a function in U-mode, from M-mode, with two register arguments and one
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// register result. If the function traps, mcause/mepc indicate the trap
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// cause. Otherwise mcause is set to U-mode ecall (= 8).
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uxlen_t __attribute__((naked)) call_umode(umode_func_2a_1r f, uxlen_t a0, uxlen_t a1) {
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asm (
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"addi sp, sp, -16 \n"
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"sw s0, 0(sp) \n"
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"sw ra, 4(sp) \n"
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// Set up mret target address and mode
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"csrw mepc, a0 \n"
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"li a0, 0x1800 \n"
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"csrc mstatus, a0 \n"
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// Set up arguments
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"mv a0, a1 \n"
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"mv a1, a2 \n"
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// Set up two return paths: trap -> mtvec, or ret -> ecall -> mtvec
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"la s0, 1f \n"
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"addi ra, s0, -4 \n"
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"csrrw s0, mtvec, s0 \n"
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// Call the function
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"mret \n"
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// Join return paths and restore mtvec
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".p2align 2 \n"
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"ecall \n"
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"1: \n"
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"csrw mtvec, s0 \n"
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// Then return via saved ra
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"lw s0, 0(sp) \n"
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"lw ra, 4(sp) \n"
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"addi sp, sp, 16 \n"
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"ret \n"
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);
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}
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void __attribute__((naked)) do_sw(uxlen_t a, uxlen_t d) {
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asm volatile (
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"sw a1, (a0)\n"
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"ecall\n"
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);
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}
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void __attribute__((naked)) do_sh(uxlen_t a, uxlen_t d) {
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asm volatile (
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"sh a1, (a0)\n"
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"ecall\n"
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);
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}
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void __attribute__((naked)) do_sb(uxlen_t a, uxlen_t d) {
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asm volatile (
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"sb a1, (a0)\n"
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"ecall\n"
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);
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}
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uxlen_t __attribute__((naked)) do_lw(uxlen_t a) {
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asm volatile (
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"lw a0, (a0)\n"
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"ecall"
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);
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}
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uxlen_t __attribute__((naked)) do_lhu(uxlen_t a) {
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asm volatile (
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"lhu a0, (a0)\n"
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"ecall"
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);
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}
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uxlen_t __attribute__((naked)) do_lbu(uxlen_t a) {
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asm volatile (
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"lbu a0, (a0)\n"
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"ecall"
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);
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}
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volatile uint32_t scratch_word;
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int main() {
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// We will keep PMP region 1 as an all-permission grant on all of memory,
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// and then use PMP region 0 to alter the permissions of only the
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// targeted scratch word.
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write_pmpcfg(1, PMPCFG_A_NAPOT << PMPCFG_A_LSB | PMPCFG_R_BITS | PMPCFG_W_BITS | PMPCFG_X_BITS);
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write_pmpaddr(1, -1u);
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write_pmpaddr(0, (uint32_t)&scratch_word >> 2);
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// Region 1 is not yet active, so we should have full permissions on this word.
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tb_puts("Initial word read/write check\n");
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scratch_word = 0;
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(void)call_umode((umode_func_2a_1r)&do_sw, (uintptr_t)&scratch_word, 0x12345678);
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tb_printf("mcause = %u\n", read_csr(mcause));
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tb_assert(scratch_word == 0x12345678, "Failed to write\n");
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uint32_t readback = call_umode((umode_func_2a_1r)&do_lw, (uintptr_t)&scratch_word, 0);
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tb_printf("mcause = %u\n", read_csr(mcause));
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tb_assert(readback == scratch_word, "Failed to read\n");
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// Change permissions to WX, and repeat previous test, making sure we get
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// the correct traps from the correct places, and trapped instructions
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// have their side effects suppressed.
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tb_puts("Remove read permission, word read/write\n");
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write_pmpcfg(0, PMPCFG_A_NA4 << PMPCFG_A_LSB | PMPCFG_W_BITS | PMPCFG_X_BITS);
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scratch_word = 0;
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(void)call_umode((umode_func_2a_1r)&do_sw, (uintptr_t)&scratch_word, 0x12345678);
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tb_printf("mcause = %u\n", read_csr(mcause));
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tb_assert(scratch_word == 0x12345678, "Failed to write\n");
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readback = call_umode((umode_func_2a_1r)&do_lw, (uintptr_t)&scratch_word, 0);
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tb_printf("mcause = %u\n", read_csr(mcause));
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tb_assert(read_csr(mepc) == (uint32_t)&do_lw, "Trap should come from load instruction\n");
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tb_assert(readback == (uintptr_t)&scratch_word, "Load instruction should not have written back\n");
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// Now again, with permissions set to RX.
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tb_puts("Restore read permission, remove write permission, word read/write\n");
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write_pmpcfg(0, PMPCFG_A_NA4 << PMPCFG_A_LSB | PMPCFG_R_BITS | PMPCFG_X_BITS);
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scratch_word = 0xdeadbeefu;
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(void)call_umode((umode_func_2a_1r)&do_sw, (uintptr_t)&scratch_word, 0x12345678);
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tb_printf("mcause = %u\n", read_csr(mcause));
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tb_assert(read_csr(mepc) == (uint32_t)&do_sw, "Trap should come from store instruction\n");
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tb_assert(scratch_word == 0xdeadbeefu, "Should not have written to memory\n");
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readback = call_umode((umode_func_2a_1r)&do_lw, (uintptr_t)&scratch_word, 0);
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tb_printf("mcause = %u\n", read_csr(mcause));
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tb_assert(readback == scratch_word, "Failed to read\n");
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// Repeat previous two tests with halfword access at top of region
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tb_puts("Remove read permission, halfword read/write\n");
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write_pmpcfg(0, PMPCFG_A_NA4 << PMPCFG_A_LSB | PMPCFG_W_BITS | PMPCFG_X_BITS);
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scratch_word = 0;
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(void)call_umode((umode_func_2a_1r)&do_sh, (uintptr_t)&scratch_word + 2, 0x12345678);
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tb_printf("mcause = %u\n", read_csr(mcause));
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tb_assert(scratch_word == 0x56780000u, "Failed to write\n");
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readback = call_umode((umode_func_2a_1r)&do_lhu, (uintptr_t)&scratch_word + 2, 0);
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tb_printf("mcause = %u\n", read_csr(mcause));
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tb_assert(read_csr(mepc) == (uint32_t)&do_lhu, "Trap should come from load instruction\n");
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tb_assert(readback == (uintptr_t)&scratch_word + 2, "Load instruction should not have written back\n");
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tb_puts("Restore read permission, remove write permission, halfword read/write\n");
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write_pmpcfg(0, PMPCFG_A_NA4 << PMPCFG_A_LSB | PMPCFG_R_BITS | PMPCFG_X_BITS);
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scratch_word = 0xdeadbeefu;
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(void)call_umode((umode_func_2a_1r)&do_sh, (uintptr_t)&scratch_word + 2, 0x12345678);
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tb_printf("mcause = %u\n", read_csr(mcause));
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tb_assert(read_csr(mepc) == (uint32_t)&do_sh, "Trap should come from store instruction\n");
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tb_assert(scratch_word == 0xdeadbeefu, "Should not have written to memory\n");
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readback = call_umode((umode_func_2a_1r)&do_lhu, (uintptr_t)&scratch_word + 2, 0);
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tb_printf("mcause = %u\n", read_csr(mcause));
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tb_assert(readback == scratch_word >> 16, "Failed to read\n");
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// Repeat previous two tests with byte access at top of region
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tb_puts("Remove read permission, byte read/write\n");
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write_pmpcfg(0, PMPCFG_A_NA4 << PMPCFG_A_LSB | PMPCFG_W_BITS | PMPCFG_X_BITS);
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scratch_word = 0;
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(void)call_umode((umode_func_2a_1r)&do_sb, (uintptr_t)&scratch_word + 3, 0x12345678);
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tb_printf("mcause = %u\n", read_csr(mcause));
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tb_assert(scratch_word == 0x78000000u, "Failed to write\n");
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readback = call_umode((umode_func_2a_1r)&do_lbu, (uintptr_t)&scratch_word + 3, 0);
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tb_printf("mcause = %u\n", read_csr(mcause));
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tb_assert(read_csr(mepc) == (uint32_t)&do_lbu, "Trap should come from load instruction\n");
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tb_assert(readback == (uintptr_t)&scratch_word + 3, "Load instruction should not have written back\n");
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tb_puts("Restore read permission, remove write permission, byte read/write\n");
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write_pmpcfg(0, PMPCFG_A_NA4 << PMPCFG_A_LSB | PMPCFG_R_BITS | PMPCFG_X_BITS);
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scratch_word = 0xdeadbeefu;
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(void)call_umode((umode_func_2a_1r)&do_sb, (uintptr_t)&scratch_word + 3, 0x12345678);
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tb_printf("mcause = %u\n", read_csr(mcause));
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tb_assert(read_csr(mepc) == (uint32_t)&do_sb, "Trap should come from store instruction\n");
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tb_assert(scratch_word == 0xdeadbeefu, "Should not have written to memory\n");
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readback = call_umode((umode_func_2a_1r)&do_lbu, (uintptr_t)&scratch_word + 3, 0);
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tb_printf("mcause = %u\n", read_csr(mcause));
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tb_assert(readback == scratch_word >> 24, "Failed to read\n");
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return 0;
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}
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@ -3,8 +3,9 @@
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// Check that U-mode execution of a wfi causes an illegal opcode exception if
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// Check that U-mode execution of a wfi causes an illegal opcode exception if
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// and only if the mstatus timeout wait bit is set.
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// and only if the mstatus timeout wait bit is set.
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// Also check that a U-mode WFI which fails PMP X check does not stall the
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//
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// procesor.
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// Also check that a U-mode WFI which fails PMP X check or TW=1 check does not
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// stall the processor.
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/*EXPECTED-OUTPUT***************************************************************
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/*EXPECTED-OUTPUT***************************************************************
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