From 723016a739af4720c2206af93b2cd3e664a3492b Mon Sep 17 00:00:00 2001 From: Luke Wren Date: Sat, 4 Dec 2021 23:49:35 +0000 Subject: [PATCH] Update ISA support in Readme --- Readme.md | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/Readme.md b/Readme.md index 31c81fb..ef95d0d 100644 --- a/Readme.md +++ b/Readme.md @@ -4,7 +4,7 @@ Hazard3 is a 3-stage RISC-V processor, implementing the `RV32I` instruction set * `M`: integer multiply/divide/modulo * `C`: compressed instructions -* `A` _(partial)_: load reserved/store conditional instructions, with AHB5 HEXCL/HEXOKAY signalling for global monitor queries +* `A` : _(experimental)_ atomic memory operations, with AHB5 global exclusives * `Zicsr`: CSR access * `Zba`: address generation * `Zbb`: basic bit manipulation @@ -24,7 +24,6 @@ _Note: the bit manipulation instructions don't have upstream compliance tests at The following are planned for future implementation: -* Complete support for the `A` extension: atomic memory operations * Debug trigger unit (breakpoint-only) Hazard3 is still under development.