From 7410c52aaca468093f7e0a8c56bb073d2d53eadd Mon Sep 17 00:00:00 2001
From: Luke Wren <wren6991@gmail.com>
Date: Fri, 26 Nov 2021 02:09:39 +0000
Subject: [PATCH] Update readme

---
 Readme.md | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Readme.md b/Readme.md
index 551fbba..e13997b 100644
--- a/Readme.md
+++ b/Readme.md
@@ -6,6 +6,7 @@ Hazard3 is a 3-stage RISC-V processor, providing the following architectural sup
 * `M` extension: integer multiply/divide/modulo
 * `C` extension: compressed instructions
 * `Zicsr` extension: CSR access
+* Tentatively the `Zba`, `Zbb`, `Zbc` and `Zbs` bitmanip extensions, though there are no upstream compliance tests for these as of yet
 * M-mode privileged instructions `ECALL`, `EBREAK`, `MRET`
 * The machine-mode (M-mode) privilege state, and standard M-mode CSRs
 * Debug support, compliant with RISC-V debug specification version 0.13.2