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Fix verilator lint width issues in triggers, PMP, DM. 

There was one genuine issue introduced by PPA changes in 78a5cb98e which
affected instruction injection on multiple harts from the DM (indicating
SMP debug testing needs to be part of regular automated regressions,
instead of semi-manual...). The rest are cosmetic.
This commit is contained in:
Luke Wren 2024-05-29 15:20:50 +01:00
parent 0b027390fa
commit 799f4f2c26
3 changed files with 17 additions and 16 deletions
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10
hdl/debug/dm/hazard3_dm.v
View File

@ -357,8 +357,8 @@ always @ (posedge clk or negedge rst_n) begin
// a sbdata0 read with sbautoincrement=1 and sbreadondata=0, but
// this seems to be a typo, fixed in later versions.
sbaddress <= sbaddress + (
sbaccess[1:0] == 2'b00 ? 3'h1 :
sbaccess[1:0] == 2'b01 ? 3'h2 : 3'h4
sbaccess[1:0] == 2'b00 ? 32'd1 :
sbaccess[1:0] == 2'b01 ? 32'd2 : 32'd4
);
end
end
@ -496,7 +496,7 @@ reg [XLEN-1:0] abstract_data0;
assign hart_data0_rdata = {N_HARTS{abstract_data0}};
always @ (posedge clk or negedge rst_n) begin: update_hart_data0
integer i;
reg signed [31:0] i;
if (!rst_n) begin
abstract_data0 <= {XLEN{1'b0}};
end else if (!dmactive) begin
@ -505,7 +505,7 @@ always @ (posedge clk or negedge rst_n) begin: update_hart_data0
abstract_data0 <= dmi_pwdata;
end else begin
for (i = 0; i < N_HARTS; i = i + 1) begin
if (hartsel == i && hart_data0_wen[i] && hart_halted[i] && abstractcs_busy)
if (hartsel == i[W_HARTSEL-1:0] && hart_data0_wen[i] && hart_halted[i] && abstractcs_busy)
abstract_data0 <= hart_data0_wdata[i * XLEN +: XLEN];
end
end
@ -739,7 +739,7 @@ always @ (posedge clk or negedge rst_n) begin
end
end
wire hart_instr_data_vld_nxt = {{N_HARTS{1'b0}},
wire [N_HARTS-1:0] hart_instr_data_vld_nxt = {{N_HARTS-1{1'b0}},
acmd_state_nxt == S_ISSUE_REGREAD || acmd_state_nxt == S_ISSUE_REGWRITE || acmd_state_nxt == S_ISSUE_REGEBREAK ||
acmd_state_nxt == S_ISSUE_PROGBUF0 || acmd_state_nxt == S_ISSUE_PROGBUF1 || acmd_state_nxt == S_ISSUE_IMPEBREAK
} << hartsel;

14
hdl/hazard3_pmp.v
View File

@ -72,7 +72,7 @@ reg [W_ADDR-3:0] pmpaddr [0:PMP_REGIONS-1];
reg [PMP_REGIONS-1:0] pmpcfg_m;
always @ (posedge clk or negedge rst_n) begin: cfg_update
integer i;
reg signed [31:0] i;
if (!rst_n) begin
for (i = 0; i < PMP_REGIONS; i = i + 1) begin
pmpcfg_l[i] <= PMP_HARDWIRED[i] ? PMP_HARDWIRED_CFG[8 * i + 7] : 1'b0;
@ -87,7 +87,7 @@ always @ (posedge clk or negedge rst_n) begin: cfg_update
pmpcfg_m <= {PMP_REGIONS{1'b0}};
end else if (cfg_wen) begin
for (i = 0; i < PMP_REGIONS; i = i + 1) begin
if (cfg_addr == PMPCFG0 + i / 4 && !pmpcfg_l[i]) begin
if (cfg_addr == PMPCFG0 + i[13:2] && !pmpcfg_l[i]) begin
if (PMP_HARDWIRED[i]) begin
// Keep tied to hardwired value (but still make the "register" sensitive to clk)
pmpcfg_l[i] <= PMP_HARDWIRED_CFG[8 * i + 7];
@ -108,7 +108,7 @@ always @ (posedge clk or negedge rst_n) begin: cfg_update
cfg_wdata[i % 4 * 8 + 3 +: 2];
end
end
if (cfg_addr == PMPADDR0 + i && !pmpcfg_l[i]) begin
if (cfg_addr == PMPADDR0 + i[11:0] && !pmpcfg_l[i]) begin
if (PMP_GRAIN > 1) begin
pmpaddr[i] <= cfg_wdata[W_ADDR-3:0] | ~(~30'h0 << (PMP_GRAIN - 1));
end else begin
@ -124,10 +124,10 @@ end
always @ (*) begin: cfg_read
integer i;
reg signed [31:0] i;
cfg_rdata = {W_DATA{1'b0}};
for (i = 0; i < PMP_REGIONS; i = i + 1) begin
if (cfg_addr == PMPCFG0 + i / 4) begin
if (cfg_addr == PMPCFG0 + i[13:2]) begin
cfg_rdata[i % 4 * 8 +: 8] = {
pmpcfg_l[i],
2'b00,
@ -136,7 +136,7 @@ always @ (*) begin: cfg_read
pmpcfg_w[i],
pmpcfg_r[i]
};
end else if (cfg_addr == PMPADDR0 + i) begin
end else if (cfg_addr == PMPADDR0 + i[11:0]) begin
// If G > 1, the G-1 LSBs of pmpaddr_i are read-only-zero when
// region is OFF, and read-only-one when region is NAPOT.
if (PMP_GRAIN > 1 && !PMP_HARDWIRED[i]) begin
@ -255,7 +255,7 @@ reg i_m; // Hazard3 extension (M-mode without locking)
reg i_l;
reg i_x;
wire [W_ADDR-1:0] i_addr_hw1 = i_addr + 2'h2;
wire [W_ADDR-1:0] i_addr_hw1 = i_addr + 32'd2;
always @ (*) begin: check_i_match
integer i;

9
hdl/hazard3_triggers.v
View File

@ -55,6 +55,7 @@ end else begin: have_triggers
parameter W_TSELECT = $clog2(BREAKPOINT_TRIGGERS);
reg [W_TSELECT-1:0] tselect;
wire tselect_in_range = {{32-W_TSELECT{1'sb0}}, $signed(tselect)} < BREAKPOINT_TRIGGERS;
// Note tdata1 and mcontrol are the same CSR. tdata1 refers to the universal
// fields (type/dmode) and mcontrol refers to those fields specific to
@ -84,7 +85,7 @@ always @ (posedge clk or negedge rst_n) begin: cfg_update
end
end else if (cfg_wen && cfg_addr == TSELECT) begin
tselect <= cfg_wdata[W_TSELECT-1:0];
end else if (cfg_wen && tselect < BREAKPOINT_TRIGGERS && !(tdata1_dmode[tselect] && !d_mode)) begin
end else if (cfg_wen && tselect_in_range && !(tdata1_dmode[tselect] && !d_mode)) begin
// Handle writes to tselect-indexed registers (note writes to D-mode
// triggers in non-D-mode are ignored rather than raising an exception)
if (cfg_addr == TDATA1) begin
@ -109,7 +110,7 @@ always @ (*) begin
if (cfg_addr == TSELECT) begin
cfg_rdata = {{W_DATA-W_TSELECT{1'b0}}, tselect};
end else if (cfg_addr == TDATA1) begin
if (tselect >= BREAKPOINT_TRIGGERS) begin
if (!tselect_in_range) begin
// Nonexistent -> type=0
cfg_rdata = {W_DATA{1'b0}};
end else begin
@ -134,13 +135,13 @@ always @ (*) begin
};
end
end else if (cfg_addr == TDATA2) begin
if (tselect >= BREAKPOINT_TRIGGERS) begin
if (!tselect_in_range) begin
cfg_rdata = {W_DATA{1'b0}};
end else begin
cfg_rdata = tdata2[tselect];
end
end else if (cfg_addr == TINFO) begin
if (tselect >= BREAKPOINT_TRIGGERS) begin
if (!tselect_in_range) begin
cfg_rdata = 32'h00000001; // type = 0, no trigger
end else begin
cfg_rdata = 32'h00000004; // type = 2, address/data match