Set U RWX permission on all of memory in the U CSR readability test

test/sim/sw_testcases/csr_readable_umode.c

@@ -9,14 +9,7 @@
 #define mconfigptr 0xf15
 #define mstatush 0x310
 
-// Exceptions here are: medeleg, mideleg, tdata1, dcsr, dpc, dscratch1,
-// dscratch0, dmdata0 (custom). medeleg/mideleg are just a couple of
-// unimplemented registers sprinkled in for a sanity check, and the remainder
-// are D-mode registers.
-//
-// Note we permit reads but not writes to tselect, to work around a logic
-// error in openocd. Planning to implement triggers at some point, so this
-// oddity will vanish.
+// Everything except for the U-mode counters should trap.
 
 /*EXPECTED-OUTPUT***************************************************************
 -> exception, mcause = 2, mpp = 0 // mvendorid
@@ -315,6 +308,10 @@ int main() {
 	// Make counters accessible to U mode
 	write_csr(mcounteren, -1u);
 
+	// Give U mode RWX permission on all of memory.
+	write_csr(pmpcfg0, 0x1fu);
+	write_csr(pmpaddr0, -1u);
+
 	// Enter function in U mode, return via ebreak trampoline
 	write_csr(mstatus, read_csr(mstatus) & ~0x1800u);
 	write_csr(mepc, &read_all_csrs);

test/sim/sw_testcases/runtests

@@ -17,7 +17,7 @@ testlist = sorted(testlist)
 
 tb_build_ret = subprocess.run(
 	["make", "-C", "../tb_cxxrtl", "tb"],
-	timeout=120
+	timeout=300
 )
 if tb_build_ret.returncode != 0:
 	sys.exit("Failed.")